LC_CTRL/DMI_VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	1.300s	4.847s	131.661us	1	1	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.850s	4.951s	24.917us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.770s	4.895s	18.747us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.190s	4.740s	39.914us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.220s	4.740s	43.583us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.090s	4.895s	62.707us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.770s	4.895s	18.747us	20	20	100.00
		lc_ctrl_csr_aliasing	1.220s	4.740s	43.583us	5	5	100.00
V1		TOTAL				39	39	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	2.190s	6.129s	192.152us	1	1	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	9.770s	13.144s	404.215us	3	3	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.640s	4.422s	35.049us	7	7	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	1.310s	4.942s	137.838us	1	1	100.00
V2	lc_state_failure	lc_ctrl_state_failure	6.840s	10.494s	759.697us	1	1	100.00
V2	lc_errors	lc_ctrl_errors	7.140s	10.407s	2.094ms	3	3	100.00
V2	security_escalation	lc_ctrl_state_failure	6.840s	10.494s	759.697us	1	1	100.00
		lc_ctrl_prog_failure	1.310s	4.942s	137.838us	1	1	100.00
		lc_ctrl_errors	7.140s	10.407s	2.094ms	3	3	100.00
		lc_ctrl_security_escalation	5.860s	9.784s	287.319us	5	5	100.00
		lc_ctrl_jtag_state_failure	32.580s	35.865s	6.589ms	3	3	100.00
		lc_ctrl_jtag_prog_failure	11.370s	14.743s	2.379ms	20	20	100.00
		lc_ctrl_jtag_errors	47.120s	50.576s	2.910ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.000s	16.073s	3.269ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	20.230s	23.212s	1.345ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	11.370s	14.743s	2.379ms	20	20	100.00
		lc_ctrl_jtag_errors	47.120s	50.576s	2.910ms	20	20	100.00
		lc_ctrl_jtag_access	5.060s	8.095s	607.594us	3	3	100.00
		lc_ctrl_jtag_regwen_during_op	22.450s	26.221s	9.591ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.320s	7.330s	280.332us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.940s	6.578s	363.966us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	20.660s	24.582s	3.089ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	19.640s	24.126s	5.712ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.200s	5.030s	133.245us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.620s	5.761s	1.504ms	3	3	100.00
		lc_ctrl_jtag_alert_test	1.290s	5.082s	245.722us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.150s	18.137s	1.059ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	0.650s	4.809s	18.075us	3	3	100.00
V2	stress_all	lc_ctrl_stress_all	2.893m	2.951m	10.463ms	8	8	100.00
V2	alert_test	lc_ctrl_alert_test	0.880s	4.678s	29.344us	3	3	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.470s	7.126s	135.552us	3	3	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.470s	7.126s	135.552us	3	3	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.850s	4.951s	24.917us	5	5	100.00
		lc_ctrl_csr_rw	0.770s	4.895s	18.747us	20	20	100.00
		lc_ctrl_csr_aliasing	1.220s	4.740s	43.583us	5	5	100.00
		lc_ctrl_same_csr_outstanding	0.970s	4.896s	20.878us	3	3	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.850s	4.951s	24.917us	5	5	100.00
		lc_ctrl_csr_rw	0.770s	4.895s	18.747us	20	20	100.00
		lc_ctrl_csr_aliasing	1.220s	4.740s	43.583us	5	5	100.00
		lc_ctrl_same_csr_outstanding	0.970s	4.896s	20.878us	3	3	100.00
V2		TOTAL				210	210	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	6.730s	10.725s	218.696us	3	3	100.00
		lc_ctrl_tl_intg_err	3.740s	8.166s	1.002ms	16	16	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.740s	8.166s	1.002ms	16	16	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	9.770s	13.144s	404.215us	3	3	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	6.840s	10.494s	759.697us	1	1	100.00
		lc_ctrl_sec_cm	6.730s	10.725s	218.696us	3	3	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	6.840s	10.494s	759.697us	1	1	100.00
		lc_ctrl_sec_cm	6.730s	10.725s	218.696us	3	3	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	6.840s	10.494s	759.697us	1	1	100.00
		lc_ctrl_sec_cm	6.730s	10.725s	218.696us	3	3	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	6.840s	10.494s	759.697us	1	1	100.00
		lc_ctrl_sec_cm	6.730s	10.725s	218.696us	3	3	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	6.840s	10.494s	759.697us	1	1	100.00
		lc_ctrl_sec_cm	6.730s	10.725s	218.696us	3	3	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	6.840s	10.494s	759.697us	1	1	100.00
		lc_ctrl_sec_cm	6.730s	10.725s	218.696us	3	3	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	6.840s	10.494s	759.697us	1	1	100.00
		lc_ctrl_sec_cm	6.730s	10.725s	218.696us	3	3	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	6.840s	10.494s	759.697us	1	1	100.00
		lc_ctrl_sec_cm	6.730s	10.725s	218.696us	3	3	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	5.860s	9.784s	287.319us	5	5	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	2.190s	6.129s	192.152us	1	1	100.00
		lc_ctrl_jtag_state_post_trans	20.230s	23.212s	1.345ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	6.270s	10.217s	2.356ms	4	4	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	6.270s	10.217s	2.356ms	4	4	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	4.340s	7.920s	2.150ms	1	1	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	6.060s	9.070s	333.934us	3	3	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	6.060s	9.070s	333.934us	3	3	100.00
V2S		TOTAL				27	27	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.079m	2.142m	13.460ms	4	6	66.67
V3		TOTAL				4	6	66.67
		TOTAL				280	282	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.96	97.87	82.75	90.03	97.67	96.85	96.13	96.40

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.42012431791807669491198868526035886999240706497174733468356046985560827651414
      Line 877, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 715574540 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 715574540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.45693698061186941733856992821107208228465175458616083828477556947711582303091
      Line 5067, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9219337300 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9219337300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---