LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.050s	9.375s	148.608us	3	3	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.700s	4.578s	15.396us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.820s	4.702s	16.237us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.030s	5.697s	95.977us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	0.920s	4.616s	19.126us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.090s	4.836s	27.731us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.820s	4.702s	16.237us	20	20	100.00
		lc_ctrl_csr_aliasing	0.920s	4.616s	19.126us	5	5	100.00
V1		TOTAL				58	58	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	2.050s	5.202s	62.318us	1	1	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	13.010s	16.958s	7.597ms	3	3	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.670s	4.443s	13.703us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	2.670s	6.235s	1.848ms	1	1	100.00
V2	lc_state_failure	lc_ctrl_state_failure	9.580s	12.771s	1.315ms	4	4	100.00
V2	lc_errors	lc_ctrl_errors	7.610s	11.517s	1.392ms	3	3	100.00
V2	security_escalation	lc_ctrl_state_failure	9.580s	12.771s	1.315ms	4	4	100.00
		lc_ctrl_prog_failure	2.670s	6.235s	1.848ms	1	1	100.00
		lc_ctrl_errors	7.610s	11.517s	1.392ms	3	3	100.00
		lc_ctrl_security_escalation	4.680s	8.466s	3.515ms	4	4	100.00
		lc_ctrl_jtag_state_failure	24.530s	28.373s	2.161ms	3	3	100.00
		lc_ctrl_jtag_prog_failure	10.470s	13.617s	2.712ms	20	20	100.00
		lc_ctrl_jtag_errors	53.730s	56.904s	3.110ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.430s	16.864s	3.448ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	14.740s	18.732s	8.542ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	10.470s	13.617s	2.712ms	20	20	100.00
		lc_ctrl_jtag_errors	53.730s	56.904s	3.110ms	19	20	95.00
		lc_ctrl_jtag_access	4.250s	7.370s	217.975us	3	3	100.00
		lc_ctrl_jtag_regwen_during_op	24.300s	27.795s	2.679ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	1.820s	5.577s	197.797us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.080s	5.635s	108.775us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	20.460s	24.334s	1.345ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	7.140s	10.537s	428.536us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	0.910s	4.668s	47.827us	3	3	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.420s	5.765s	119.660us	3	3	100.00
		lc_ctrl_jtag_alert_test	1.710s	5.710s	87.697us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	4.360s	8.350s	940.883us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	0.630s	4.256s	29.733us	3	3	100.00
V2	stress_all	lc_ctrl_stress_all	3.903m	3.965m	12.376ms	6	6	100.00
V2	alert_test	lc_ctrl_alert_test	0.670s	4.255s	55.198us	3	3	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	1.680s	5.708s	229.908us	3	3	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	1.680s	5.708s	229.908us	3	3	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.700s	4.578s	15.396us	5	5	100.00
		lc_ctrl_csr_rw	0.820s	4.702s	16.237us	20	20	100.00
		lc_ctrl_csr_aliasing	0.920s	4.616s	19.126us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.370s	4.825s	68.031us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.700s	4.578s	15.396us	5	5	100.00
		lc_ctrl_csr_rw	0.820s	4.702s	16.237us	20	20	100.00
		lc_ctrl_csr_aliasing	0.920s	4.616s	19.126us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.370s	4.825s	68.031us	20	20	100.00
V2		TOTAL				222	223	99.55
V2S	tl_intg_err	lc_ctrl_sec_cm	6.900s	10.559s	242.078us	3	3	100.00
		lc_ctrl_tl_intg_err	2.570s	6.856s	128.363us	19	19	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	2.570s	6.856s	128.363us	19	19	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	13.010s	16.958s	7.597ms	3	3	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	9.580s	12.771s	1.315ms	4	4	100.00
		lc_ctrl_sec_cm	6.900s	10.559s	242.078us	3	3	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	9.580s	12.771s	1.315ms	4	4	100.00
		lc_ctrl_sec_cm	6.900s	10.559s	242.078us	3	3	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	9.580s	12.771s	1.315ms	4	4	100.00
		lc_ctrl_sec_cm	6.900s	10.559s	242.078us	3	3	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	9.580s	12.771s	1.315ms	4	4	100.00
		lc_ctrl_sec_cm	6.900s	10.559s	242.078us	3	3	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	9.580s	12.771s	1.315ms	4	4	100.00
		lc_ctrl_sec_cm	6.900s	10.559s	242.078us	3	3	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	9.580s	12.771s	1.315ms	4	4	100.00
		lc_ctrl_sec_cm	6.900s	10.559s	242.078us	3	3	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	9.580s	12.771s	1.315ms	4	4	100.00
		lc_ctrl_sec_cm	6.900s	10.559s	242.078us	3	3	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	9.580s	12.771s	1.315ms	4	4	100.00
		lc_ctrl_sec_cm	6.900s	10.559s	242.078us	3	3	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	4.680s	8.466s	3.515ms	4	4	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	2.050s	5.202s	62.318us	1	1	100.00
		lc_ctrl_jtag_state_post_trans	14.740s	18.732s	8.542ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	5.630s	9.409s	943.294us	4	4	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	5.630s	9.409s	943.294us	4	4	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	5.480s	9.431s	262.484us	1	1	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	7.170s	10.917s	453.134us	3	3	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	7.170s	10.917s	453.134us	3	3	100.00
V2S		TOTAL				30	30	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.084m	1.138m	12.839ms	3	5	60.00
V3		TOTAL				3	5	60.00
		TOTAL				313	316	99.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.88	97.26	81.92	88.25	76.60	94.27	94.27	96.62

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 2.lc_ctrl_jtag_errors.56287858744884992769244858794550708788197537199182766545110447180055593822412
      Line 2532, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 1543395897 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1543395897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.30360772939135399056097662265956592215805428108629524312496464947463302743257
      Line 2416, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12838818294 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 12838818294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.88548535789501141363982042201328294529626027715872192949695514991018684919989
      Line 2992, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1790382888 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1790382888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---