LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	2.780s	6.364s	107.968us	3	3	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.700s	4.828s	26.565us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.680s	4.380s	22.773us	3	3	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.070s	5.645s	1.105ms	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	0.800s	4.600s	65.938us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.580s	4.859s	68.351us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.680s	4.380s	22.773us	3	3	100.00
		lc_ctrl_csr_aliasing	0.800s	4.600s	65.938us	5	5	100.00
V1		TOTAL				41	41	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	3.520s	7.260s	85.352us	1	1	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	10.820s	14.800s	1.203ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.690s	4.243s	13.800us	7	7	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	2.070s	5.302s	66.210us	3	3	100.00
V2	lc_state_failure	lc_ctrl_state_failure	8.270s	11.471s	2.571ms	1	1	100.00
V2	lc_errors	lc_ctrl_errors	8.930s	12.626s	1.824ms	4	4	100.00
V2	security_escalation	lc_ctrl_state_failure	8.270s	11.471s	2.571ms	1	1	100.00
		lc_ctrl_prog_failure	2.070s	5.302s	66.210us	3	3	100.00
		lc_ctrl_errors	8.930s	12.626s	1.824ms	4	4	100.00
		lc_ctrl_security_escalation	8.640s	12.628s	844.049us	4	4	100.00
		lc_ctrl_jtag_state_failure	31.370s	34.678s	1.493ms	4	4	100.00
		lc_ctrl_jtag_prog_failure	11.670s	15.470s	2.692ms	20	20	100.00
		lc_ctrl_jtag_errors	22.400s	26.126s	11.220ms	3	3	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.700s	12.705s	606.342us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	16.260s	20.155s	800.270us	20	20	100.00
		lc_ctrl_jtag_prog_failure	11.670s	15.470s	2.692ms	20	20	100.00
		lc_ctrl_jtag_errors	22.400s	26.126s	11.220ms	3	3	100.00
		lc_ctrl_jtag_access	7.700s	11.316s	1.740ms	3	3	100.00
		lc_ctrl_jtag_regwen_during_op	23.820s	27.062s	5.046ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.420s	6.804s	429.497us	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.680s	5.596s	81.057us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	17.530s	20.796s	1.480ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.460s	17.352s	3.609ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.190s	4.565s	141.674us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	1.700s	5.919s	472.488us	4	4	100.00
		lc_ctrl_jtag_alert_test	1.330s	4.594s	251.119us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.070s	22.981s	1.277ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	0.870s	4.269s	69.559us	3	3	100.00
V2	stress_all	lc_ctrl_stress_all	5.371m	5.434m	60.868ms	6	6	100.00
V2	alert_test	lc_ctrl_alert_test	0.750s	4.214s	125.779us	3	3	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	2.470s	5.687s	96.615us	4	4	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	2.470s	5.687s	96.615us	4	4	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.700s	4.828s	26.565us	5	5	100.00
		lc_ctrl_csr_rw	0.680s	4.380s	22.773us	3	3	100.00
		lc_ctrl_csr_aliasing	0.800s	4.600s	65.938us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.350s	4.899s	48.717us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.700s	4.828s	26.565us	5	5	100.00
		lc_ctrl_csr_rw	0.680s	4.380s	22.773us	3	3	100.00
		lc_ctrl_csr_aliasing	0.800s	4.600s	65.938us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.350s	4.899s	48.717us	20	20	100.00
V2		TOTAL				220	220	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	6.660s	10.438s	910.119us	3	3	100.00
		lc_ctrl_tl_intg_err	2.930s	6.844s	316.919us	18	18	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	2.930s	6.844s	316.919us	18	18	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	10.820s	14.800s	1.203ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	8.270s	11.471s	2.571ms	1	1	100.00
		lc_ctrl_sec_cm	6.660s	10.438s	910.119us	3	3	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	8.270s	11.471s	2.571ms	1	1	100.00
		lc_ctrl_sec_cm	6.660s	10.438s	910.119us	3	3	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	8.270s	11.471s	2.571ms	1	1	100.00
		lc_ctrl_sec_cm	6.660s	10.438s	910.119us	3	3	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	8.270s	11.471s	2.571ms	1	1	100.00
		lc_ctrl_sec_cm	6.660s	10.438s	910.119us	3	3	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	8.270s	11.471s	2.571ms	1	1	100.00
		lc_ctrl_sec_cm	6.660s	10.438s	910.119us	3	3	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	8.270s	11.471s	2.571ms	1	1	100.00
		lc_ctrl_sec_cm	6.660s	10.438s	910.119us	3	3	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	8.270s	11.471s	2.571ms	1	1	100.00
		lc_ctrl_sec_cm	6.660s	10.438s	910.119us	3	3	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	8.270s	11.471s	2.571ms	1	1	100.00
		lc_ctrl_sec_cm	6.660s	10.438s	910.119us	3	3	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	8.640s	12.628s	844.049us	4	4	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	3.520s	7.260s	85.352us	1	1	100.00
		lc_ctrl_jtag_state_post_trans	16.260s	20.155s	800.270us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	6.720s	10.423s	480.487us	4	4	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	6.720s	10.423s	480.487us	4	4	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	4.830s	8.312s	357.830us	1	1	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	5.770s	9.289s	592.861us	3	3	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	5.770s	9.289s	592.861us	3	3	100.00
V2S		TOTAL				29	29	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.177m	1.241m	3.823ms	6	8	75.00
V3		TOTAL				6	8	75.00
		TOTAL				296	298	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.92	97.24	82.04	88.25	76.84	94.21	94.41	96.44

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.106478165101775302623652179737111110102486073066112458747828659759738372552126
      Line 835, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2734074743 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2734074743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.75931419804646659663664000226109060652047591940837190206857744746642983016187
      Line 10348, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4165253454 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 4165253454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---