2aab100d17| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 1.356m | 1.418m | 6.344ms | 3 | 3 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 0.490s | 4.674s | 13.955us | 3 | 3 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 0.500s | 4.714s | 13.972us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 2.170s | 6.987s | 448.660us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 0.690s | 5.782s | 32.721us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 0.860s | 4.709s | 82.362us | 1 | 3 | 33.33 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 0.500s | 4.714s | 13.972us | 20 | 20 | 100.00 |
| mbx_csr_aliasing | 0.690s | 5.782s | 32.721us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 37 | 39 | 94.87 | ||||
| V2 | mbx_stress | mbx_stress | 4.070s | 7.211s | 363.459us | 0 | 1 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 1.087m | 1.150m | 11.955ms | 1 | 1 | 100.00 |
| V2 | mbx_stress_all | mbx_stress_all | 0 | 0 | -- | |||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 48.980s | 52.146s | 49.237ms | 3 | 4 | 75.00 |
| V2 | mbx_range_lock | 0 | 0 | -- | ||||
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 15.710s | 20.263s | 3.571ms | 3 | 3 | 100.00 |
| V2 | alert_test | mbx_alert_test | 0.490s | 3.628s | 17.468us | 3 | 3 | 100.00 |
| V2 | intr_test | mbx_intr_test | 0.540s | 4.677s | 153.410us | 5 | 5 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 1.390s | 4.698s | 58.881us | 2 | 5 | 40.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 1.390s | 4.698s | 58.881us | 2 | 5 | 40.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 0.490s | 4.674s | 13.955us | 3 | 3 | 100.00 |
| mbx_csr_rw | 0.500s | 4.714s | 13.972us | 20 | 20 | 100.00 | ||
| mbx_csr_aliasing | 0.690s | 5.782s | 32.721us | 5 | 5 | 100.00 | ||
| mbx_same_csr_outstanding | 0.520s | 5.783s | 125.046us | 3 | 3 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 0.490s | 4.674s | 13.955us | 3 | 3 | 100.00 |
| mbx_csr_rw | 0.500s | 4.714s | 13.972us | 20 | 20 | 100.00 | ||
| mbx_csr_aliasing | 0.690s | 5.782s | 32.721us | 5 | 5 | 100.00 | ||
| mbx_same_csr_outstanding | 0.520s | 5.783s | 125.046us | 3 | 3 | 100.00 | ||
| V2 | TOTAL | 20 | 25 | 80.00 | ||||
| V2S | tl_intg_err | mbx_tl_intg_err | 1.430s | 5.857s | 522.625us | 9 | 9 | 100.00 |
| mbx_sec_cm | 0.420s | 3.638s | 11.552us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | |||
| V2S | sec_cm_address_range_config_regwen_mubi | sec_cm_address_range_config_regwen_mubi | 0 | 0 | -- | |||
| V2S | TOTAL | 14 | 14 | 100.00 | ||||
| V3 | stress_all_with_rand_reset | mbx_stress_all_with_rand_reset | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 0 | -- | ||||
| TOTAL | 71 | 78 | 91.03 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 10 | 8 | 5 | 50.00 |
| V2S | 4 | 2 | 2 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 84.20 | 95.61 | 90.78 | 81.54 | 42.11 | 90.37 | 97.15 | 91.84 |
| Target | Elapsed |
|---|---|
| build | 00:06:40 |
| run | 14:15:03 |
| cov_merge | 14:15:15 |
| cov_report | 14:15:22 |
| Total | 14:15:22 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 2 failures:
Test mbx_stress has 1 failures.
0.mbx_stress.43163848721949537129171824679773266122023140222264686616648860008173731895831
Line 528, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/mbx-sim-vcs/0.mbx_stress/latest/run.log
UVM_ERROR @ 363458842 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 363458842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_imbx_oob has 1 failures.
3.mbx_imbx_oob.87832673495021152342770318324480131493714934902899075023486282036395319001368
Line 86, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/mbx-sim-vcs/3.mbx_imbx_oob/latest/run.log
UVM_ERROR @ 86347955 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 86347955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@9517) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.mbx_csr_mem_rw_with_rand_reset.105764965006812802504781198855432742652345286874260020663119518510864598845508
Line 80, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/mbx-sim-vcs/1.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 18384993 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@9517) { a_addr: 'h9fdb79b0 a_data: 'heeea5750 a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'h8a a_opcode: 'h1 a_user: 'h26d49 a_blocked: 'h0 d_param: 'h0 d_source: 'h8a d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 18384993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@4965) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.mbx_tl_errors.17933406546941630015052768727965747800437246880672146258509102612592955247416
Line 79, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/mbx-sim-vcs/2.mbx_tl_errors/latest/run.log
UVM_ERROR @ 18570456 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@4965) { a_addr: 'hb9b57db0 a_data: 'h584f6e0f a_mask: 'h0 a_size: 'h2 a_param: 'h0 a_source: 'he4 a_opcode: 'h1 a_user: 'h27acd a_blocked: 'h0 d_param: 'h0 d_source: 'he4 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 18570456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@5997) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.mbx_csr_mem_rw_with_rand_reset.20290827035989603191270158411122604271196775936328368712341351334995919981359
Line 80, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/mbx-sim-vcs/2.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 6019309 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@5997) { a_addr: 'h7406d450 a_data: 'hc540b9f6 a_mask: 'h2 a_size: 'h2 a_param: 'h0 a_source: 'he4 a_opcode: 'h1 a_user: 'h26de2 a_blocked: 'h0 d_param: 'h0 d_source: 'he4 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 6019309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@4913) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.mbx_tl_errors.39732812461383653538997511558515860958840673933909099671211518484144677548375
Line 79, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/mbx-sim-vcs/3.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1768676 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@4913) { a_addr: 'hc2cc86b4 a_data: 'hf4742432 a_mask: 'he a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h1 a_user: 'h27e10 a_blocked: 'h0 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 1768676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@3681) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.mbx_tl_errors.67543806102052458593482999938285252572739319728862630287629267310195569398709
Line 79, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/mbx-sim-vcs/4.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1188908 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@3681) { a_addr: 'h570984f0 a_data: 'hbdf294ac a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'h96 a_opcode: 'h1 a_user: 'h249e4 a_blocked: 'h0 d_param: 'h0 d_source: 'h96 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 1188908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---