OTP_CTRL/DRAGONFLY Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.620s	5.327s	215.074us	4	4	100.00
V1	smoke	otp_ctrl_smoke	5.300s	9.052s	2.807ms	1	1	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.830s	6.793s	1.871ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.780s	5.999s	758.689us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	5.850s	9.544s	702.879us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	13.540s	16.577s	7.948ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	2.460s	6.034s	1.359ms	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.780s	5.999s	758.689us	20	20	100.00
		otp_ctrl_csr_aliasing	13.540s	16.577s	7.948ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.540s	4.901s	628.939us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.290s	4.889s	91.912us	5	5	100.00
V1		TOTAL				53	53	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	1.984m	2.050m	10.762ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	6.030s	9.353s	3.179ms	45	45	100.00
V2	partition_check	otp_ctrl_background_chks	25.610s	29.418s	6.575ms	10	10	100.00
		otp_ctrl_check_fail	45.440s	49.236s	12.025ms	16	20	80.00
V2	regwen_during_otp_init	otp_ctrl_regwen	10.720s	13.771s	1.806ms	13	13	100.00
V2	partition_lock	otp_ctrl_dai_lock	24.270s	27.985s	5.206ms	8	8	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.108m	1.173m	33.809ms	10	10	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	35.690s	39.080s	16.026ms	8	8	100.00
		otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	30.280s	34.166s	19.550ms	3	3	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.510m	1.571m	21.453ms	13	14	92.86
V2	test_access	otp_ctrl_test_access	49.080s	52.157s	25.633ms	11	11	100.00
V2	stress_all	otp_ctrl_stress_all	15.627m	15.687m	356.128ms	41	41	100.00
V2	intr_test	otp_ctrl_intr_test	2.090s	5.854s	668.526us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	1.810s	5.268s	241.032us	3	3	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.160s	9.688s	913.882us	7	7	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.160s	9.688s	913.882us	7	7	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.830s	6.793s	1.871ms	5	5	100.00
		otp_ctrl_csr_rw	1.780s	5.999s	758.689us	20	20	100.00
		otp_ctrl_csr_aliasing	13.540s	16.577s	7.948ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.480s	8.433s	1.637ms	3	3	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.830s	6.793s	1.871ms	5	5	100.00
		otp_ctrl_csr_rw	1.780s	5.999s	758.689us	20	20	100.00
		otp_ctrl_csr_aliasing	13.540s	16.577s	7.948ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.480s	8.433s	1.637ms	3	3	100.00
V2		TOTAL				274	279	98.21
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
		otp_ctrl_tl_intg_err	26.160s	29.732s	6.490ms	8	8	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	26.160s	29.732s	6.490ms	8	8	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	5.300s	9.052s	2.807ms	1	1	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	5.300s	9.052s	2.807ms	1	1	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
		otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
		otp_ctrl_macro_errs	1.510m	1.571m	21.453ms	13	14	92.86
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
		otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
		otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
		otp_ctrl_macro_errs	1.510m	1.571m	21.453ms	13	14	92.86
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.840s	38.606s	7.048ms	32	32	100.00
		otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	6.030s	9.353s	3.179ms	45	45	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	45.440s	49.236s	12.025ms	16	20	80.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	24.270s	27.985s	5.206ms	8	8	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	24.270s	27.985s	5.206ms	8	8	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	24.270s	27.985s	5.206ms	8	8	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	24.270s	27.985s	5.206ms	8	8	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	24.270s	27.985s	5.206ms	8	8	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	5.300s	9.052s	2.807ms	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	24.270s	27.985s	5.206ms	8	8	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	5.300s	9.052s	2.807ms	1	1	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.606m	6.660m	89.151ms	4	5	80.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	10.720s	13.771s	1.806ms	13	13	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	5.300s	9.052s	2.807ms	1	1	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	5.300s	9.052s	2.807ms	1	1	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.510m	1.571m	21.453ms	13	14	92.86
V2S		TOTAL				12	13	92.31
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	1.770m	1.839m	75.113ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.881m	2.943m	86.717ms	53	100	53.00
V3		TOTAL				54	101	53.47
	Unmapped tests	otp_ctrl_zeroization	4.570s	8.417s	1.004ms	16	16	100.00
		otp_ctrl_zeroization_with_checks	9.920s	13.290s	3.775ms	25	25	100.00
		TOTAL				434	487	89.12

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	2	100.00
V1	9	9	9	100.00
V2	17	17	15	88.24
V2S	2	2	1	50.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.67	94.99	93.59	93.14	59.95	93.45	93.40	85.17

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1664) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 13 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 13 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.34658099079119726543585090832734558359648840961582445870871132614206169689217
      Line 97, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 536931773 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 536931773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.otp_ctrl_stress_all_with_rand_reset.101414432947018651253839901562740636226733531292268901188720404894598857824619
      Line 97, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  67847985 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @  67847985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1664) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 12 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 6.otp_ctrl_stress_all_with_rand_reset.56262108304157851483248182735442780931433165907392010636197227248042246050801
      Line 132, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9848247705 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (490730979 [0x1d3ff5e3] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 9848247705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.otp_ctrl_stress_all_with_rand_reset.99033522586384144661530235286890706702931138267953567294913264847884284164193
      Line 154, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5934905453 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2859936918 [0xaa772c96] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 5934905453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

  • Test otp_ctrl_macro_errs has 1 failures.

    • 10.otp_ctrl_macro_errs.93724069558069065714062573049134373294507878201880369251671596833553892213813
      Line 99, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/10.otp_ctrl_macro_errs/latest/run.log

        UVM_ERROR @ 979232616 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 514 [0x202]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 979232616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_check_fail has 4 failures.

    • 14.otp_ctrl_check_fail.63666944149990069019436507777036903907913086685757626396981611143888802991199
      Line 96, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/14.otp_ctrl_check_fail/latest/run.log

        UVM_ERROR @ 880160128 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 880160128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 16.otp_ctrl_check_fail.98351750160173022977879888931512737239209712376406938396981065544223805259534
      Line 98, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/16.otp_ctrl_check_fail/latest/run.log

        UVM_ERROR @ 14522628360 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2 [0x2]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 14522628360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1664) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* has 9 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 9 failures.

    • 3.otp_ctrl_stress_all_with_rand_reset.91726114725939748751712665590738500278830149577518897242168552956703539839613
      Line 118, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 720625613 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_26
        UVM_INFO @ 720625613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 18.otp_ctrl_stress_all_with_rand_reset.106328190029459750939852329293856357431871381176549953245894098947126085575678
      Line 128, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 946356510 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.err_code_26
        UVM_INFO @ 946356510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (cip_base_vseq.sv:1316) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! has 8 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 8 failures.

    • 32.otp_ctrl_stress_all_with_rand_reset.52640935097294216709828205876514637119233820891437000914906867146040771440484
      Line 134, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2701398550 ps: (cip_base_vseq.sv:1316) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
        UVM_INFO @ 2701398550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.otp_ctrl_stress_all_with_rand_reset.23695299182790920340895201321087809927125075312052784668799189313022985131342
      Line 131, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9426568089 ps: (cip_base_vseq.sv:1316) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
        UVM_INFO @ 9426568089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:617) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * has 3 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 35.otp_ctrl_stress_all_with_rand_reset.7552243096960809807337604999990576336635046201636092054797922480535642135594
      Line 96, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  36655992 ps: (cip_base_scoreboard.sv:617) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
        UVM_INFO @  36655992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.otp_ctrl_stress_all_with_rand_reset.60935617106624536450475652811278070407119025430635502626373442720490138835666
      Line 96, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  93478815 ps: (cip_base_scoreboard.sv:617) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
        UVM_INFO @  93478815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (otp_ctrl_base_vseq.sv:266) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 3 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 47.otp_ctrl_stress_all_with_rand_reset.107378125240692220062745348572780611082672200617328990980751665077336910551761
      Line 126, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2716455498 ps: (otp_ctrl_base_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 896 [0x380]) dai addr 380 rdata0 readout mismatch
        UVM_INFO @ 2716455498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 68.otp_ctrl_stress_all_with_rand_reset.99634410223624627423096033797302696811531787123750956227529446919861339613960
      Line 115, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13690373708 ps: (otp_ctrl_base_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1296 [0x510]) dai addr 510 rdata0 readout mismatch
        UVM_INFO @ 13690373708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:343) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 5.otp_ctrl_stress_all_with_rand_reset.53396232014666453134333637958464856157021705814010661491643184646138203822945
      Line 125, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 253081240 ps: (otp_ctrl_scoreboard.sv:343) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 253081240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 80.otp_ctrl_stress_all_with_rand_reset.33225313404715360207293149286138106393757398029593027166867675421927985807671
      Line 139, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26941923314 ps: (otp_ctrl_scoreboard.sv:343) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 26941923314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test otp_ctrl_sec_cm has 1 failures.

    • 4.otp_ctrl_sec_cm.113403443621630203810696103715307711980998182309495388433107457500091839177582
      Line 2291, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/4.otp_ctrl_sec_cm/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((lc_dft_en_i == On) || (cio_test_en_o == *))' has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.otp_ctrl_stress_all_with_rand_reset.4710762927463415554410575924706136821039179258364068046112276284309718409710
      Line 146, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '((lc_dft_en_i == On) || (cio_test_en_o == 0))'
        UVM_ERROR @ 1917811935 ps: (otp_ctrl_if.sv:418) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 1917811935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:266) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr cbc rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 85.otp_ctrl_stress_all_with_rand_reset.1200329600288310270547824600933713311474860138365327027588939522330933850974
      Line 113, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6439243173 ps: (otp_ctrl_base_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 3256 [0xcb8]) dai addr cbc rdata0 readout mismatch
        UVM_INFO @ 6439243173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---