OTP_CTRL/EGRET Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.170s	5.381s	200.422us	4	4	100.00
V1	smoke	otp_ctrl_smoke	11.560s	15.516s	8.812ms	1	1	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.020s	5.932s	993.412us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.290s	4.945s	493.684us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.450s	12.042s	8.049ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	2.950s	7.259s	194.366us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.120s	7.073s	1.648ms	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.290s	4.945s	493.684us	20	20	100.00
		otp_ctrl_csr_aliasing	2.950s	7.259s	194.366us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	0.920s	4.884s	74.756us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	0.970s	4.875s	565.960us	5	5	100.00
V1		TOTAL				53	53	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	10.800s	15.485s	315.836us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	4.500s	8.106s	1.819ms	29	29	100.00
V2	partition_check	otp_ctrl_background_chks	19.730s	22.947s	23.436ms	3	3	100.00
		otp_ctrl_check_fail	26.330s	30.365s	7.565ms	12	12	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	6.970s	10.945s	4.641ms	6	6	100.00
V2	partition_lock	otp_ctrl_dai_lock	30.820s	33.945s	15.020ms	6	6	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	23.210s	26.303s	5.003ms	7	7	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	15.270s	18.647s	822.833us	6	6	100.00
		otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	24.530s	27.854s	1.566ms	4	4	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	16.130s	20.023s	1.146ms	7	7	100.00
V2	test_access	otp_ctrl_test_access	15.800s	19.496s	5.067ms	7	7	100.00
V2	stress_all	otp_ctrl_stress_all	3.427m	3.479m	41.118ms	21	21	100.00
V2	intr_test	otp_ctrl_intr_test	1.550s	5.135s	632.073us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	1.450s	5.408s	215.278us	3	3	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	5.840s	9.747s	2.456ms	5	5	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	5.840s	9.747s	2.456ms	5	5	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.020s	5.932s	993.412us	5	5	100.00
		otp_ctrl_csr_rw	1.290s	4.945s	493.684us	20	20	100.00
		otp_ctrl_csr_aliasing	2.950s	7.259s	194.366us	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.150s	5.190s	112.482us	3	3	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.020s	5.932s	993.412us	5	5	100.00
		otp_ctrl_csr_rw	1.290s	4.945s	493.684us	20	20	100.00
		otp_ctrl_csr_aliasing	2.950s	7.259s	194.366us	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.150s	5.190s	112.482us	3	3	100.00
V2		TOTAL				188	188	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	tl_intg_err	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
		otp_ctrl_tl_intg_err	29.310s	33.137s	19.141ms	11	11	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	prim_fsm_check	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	29.310s	33.137s	19.141ms	11	11	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	11.560s	15.516s	8.812ms	1	1	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	11.560s	15.516s	8.812ms	1	1	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
		otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
		otp_ctrl_macro_errs	16.130s	20.023s	1.146ms	7	7	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
		otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
		otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
		otp_ctrl_macro_errs	16.130s	20.023s	1.146ms	7	7	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.160s	16.523s	870.294us	18	18	100.00
		otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	4.500s	8.106s	1.819ms	29	29	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	26.330s	30.365s	7.565ms	12	12	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	30.820s	33.945s	15.020ms	6	6	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	30.820s	33.945s	15.020ms	6	6	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	30.820s	33.945s	15.020ms	6	6	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	30.820s	33.945s	15.020ms	6	6	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	30.820s	33.945s	15.020ms	6	6	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	11.560s	15.516s	8.812ms	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	30.820s	33.945s	15.020ms	6	6	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	11.560s	15.516s	8.812ms	1	1	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	2.077m	2.136m	42.838ms	5	6	83.33
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	6.970s	10.945s	4.641ms	6	6	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	11.560s	15.516s	8.812ms	1	1	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	11.560s	15.516s	8.812ms	1	1	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	16.130s	20.023s	1.146ms	7	7	100.00
V2S		TOTAL				16	17	94.12
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.570s	17.568s	7.504ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.144m	2.203m	30.568ms	51	100	51.00
V3		TOTAL				52	101	51.49
	Unmapped tests	otp_ctrl_zeroization	3.360s	6.464s	464.622us	5	5	100.00
		otp_ctrl_zeroization_with_checks	6.260s	9.650s	2.637ms	4	4	100.00
		TOTAL				318	368	86.41

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	2	100.00
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	1	50.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.36	90.63	94.21	95.76	63.72	86.89	94.75	92.54

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1316) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! has 15 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 15 failures.

    • 9.otp_ctrl_stress_all_with_rand_reset.59438595648524420012384131667941464382406881992213156370450857749989730114954
      Line 190, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17984037570 ps: (cip_base_vseq.sv:1316) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
        UVM_INFO @ 17984037570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.otp_ctrl_stress_all_with_rand_reset.66257798068547372696060829220718604207926027087732069929484637075089545589909
      Line 101, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 736347551 ps: (cip_base_vseq.sv:1316) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
        UVM_INFO @ 736347551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1352) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 13 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 13 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.37029521374718473339482207322351322739665995002271652171176717161663321867701
      Line 132, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3896926034 ps: (otp_ctrl_scoreboard.sv:1352) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4136540590 [0xf68e99ae]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 3896926034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.otp_ctrl_stress_all_with_rand_reset.53559623460485248438085297810688762334766795001991064291517643055531818790951
      Line 222, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5704029715 ps: (otp_ctrl_scoreboard.sv:1352) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1869009913 [0x6f66d3f9] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 5704029715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1352) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 6 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

    • 7.otp_ctrl_stress_all_with_rand_reset.35414352914451216597899650672877857183622188355577505399195751955566211444664
      Line 135, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2444261364 ps: (otp_ctrl_scoreboard.sv:1352) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 2444261364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.otp_ctrl_stress_all_with_rand_reset.103534842676447835467384455976730386969105048755812460500980763748787229823139
      Line 116, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8530716369 ps: (otp_ctrl_scoreboard.sv:1352) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 8530716369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:617) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * has 4 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 10.otp_ctrl_stress_all_with_rand_reset.47870772162081316569976591930227025350402384503947743558362136708260915193590
      Line 170, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43621659778 ps: (cip_base_scoreboard.sv:617) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
        UVM_INFO @ 43621659778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 74.otp_ctrl_stress_all_with_rand_reset.80569910078788083590275945699017839180777932551509307969699011300926489303927
      Line 147, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11960318740 ps: (cip_base_scoreboard.sv:617) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
        UVM_INFO @ 11960318740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1352) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* has 4 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 15.otp_ctrl_stress_all_with_rand_reset.11907212066770057846071678768203735176034996993086794128609463600153593827541
      Line 107, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1547797745 ps: (otp_ctrl_scoreboard.sv:1352) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
        UVM_INFO @ 1547797745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 28.otp_ctrl_stress_all_with_rand_reset.18312151362812410403816202333704762214886088921031469183379034157403265099399
      Line 133, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1623275109 ps: (otp_ctrl_scoreboard.sv:1352) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
        UVM_INFO @ 1623275109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (otp_ctrl_base_vseq.sv:266) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 3 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 4.otp_ctrl_stress_all_with_rand_reset.44354533478167075867736681391266640102328201305404011381435102450627571940451
      Line 127, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6528128428 ps: (otp_ctrl_base_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1028 [0x404]) dai addr 404 rdata0 readout mismatch
        UVM_INFO @ 6528128428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 40.otp_ctrl_stress_all_with_rand_reset.28873326788106636486830567275636077302025593633837855328178478429851286263287
      Line 179, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21961763679 ps: (otp_ctrl_base_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1236271210 [0x49b0006a]) dai addr 754 rdata0 readout mismatch
        UVM_INFO @ 21961763679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:1023) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire has 1 failures:

  • Test otp_ctrl_sec_cm has 1 failures.

    • 4.otp_ctrl_sec_cm.41046005271857348880971901110566964926890015293812792870294636059523811636211
      Line 1580, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/4.otp_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 7082056959 ps: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
        UVM_INFO @ 7082056959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:266) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.otp_ctrl_stress_all_with_rand_reset.23438417894413626567936926105903789671967111710372402694632010851396080680242
      Line 148, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9635027745 ps: (otp_ctrl_base_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1488 [0x5d0]) dai addr 5d0 rdata0 readout mismatch
        UVM_INFO @ 9635027745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((lc_dft_en_i == On) || (cio_test_en_o == *))' has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.otp_ctrl_stress_all_with_rand_reset.4331593144441010856608454643903972888434834111589902861842352086846907420076
      Line 124, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '((lc_dft_en_i == On) || (cio_test_en_o == 0))'
        UVM_ERROR @ 3554455465 ps: (otp_ctrl_if.sv:300) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 3554455465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1237) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 68.otp_ctrl_stress_all_with_rand_reset.86480103477462075748689390722937402993526343287317990883047613364002613540433
      Line 105, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10732968338 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10732968338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:266) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 94.otp_ctrl_stress_all_with_rand_reset.78529786099896984092699897766768027132705079340823275233006921071614752058300
      Line 178, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/otp_ctrl_top_egret-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17713578874 ps: (otp_ctrl_base_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 92 [0x5c]) dai addr 5c rdata0 readout mismatch
        UVM_INFO @ 17713578874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---