PATTGEN Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: `2aab100d17`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.730s	7.449s	117.463us	4	4	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	0.450s	4.513s	17.831us	7	7	100.00
V1	csr_rw	pattgen_csr_rw	0.450s	4.516s	107.733us	10	10	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	1.790s	5.626s	252.783us	3	3	100.00
V1	csr_aliasing	pattgen_csr_aliasing	0.480s	4.404s	36.717us	4	4	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	0.770s	4.883s	78.659us	10	10	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	0.450s	4.516s	107.733us	10	10	100.00
		pattgen_csr_aliasing	0.480s	4.404s	36.717us	4	4	100.00
V1		TOTAL				38	38	100.00
V2	perf	pattgen_perf	1.001h	1.001h		2	3	66.67
V2	cnt_rollover	cnt_rollover	52.850s	55.953s	8.049ms	5	5	100.00
V2	error	pattgen_error	0.570s	5.467s	74.059us	4	4	100.00
V2	stress_all	pattgen_stress_all	3.002h	3.002h		4	7	57.14
V2	alert_test	pattgen_alert_test	0.410s	5.346s	37.022us	3	3	100.00
V2	intr_test	pattgen_intr_test	0.450s	4.534s	29.199us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	1.570s	5.623s	114.784us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	1.570s	5.623s	114.784us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	0.450s	4.513s	17.831us	7	7	100.00
		pattgen_csr_rw	0.450s	4.516s	107.733us	10	10	100.00
		pattgen_csr_aliasing	0.480s	4.404s	36.717us	4	4	100.00
		pattgen_same_csr_outstanding	0.560s	4.751s	93.005us	26	26	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	0.450s	4.513s	17.831us	7	7	100.00
		pattgen_csr_rw	0.450s	4.516s	107.733us	10	10	100.00
		pattgen_csr_aliasing	0.480s	4.404s	36.717us	4	4	100.00
		pattgen_same_csr_outstanding	0.560s	4.751s	93.005us	26	26	100.00
V2		TOTAL				114	118	96.61
V2S	tl_intg_err	pattgen_tl_intg_err	0.940s	5.197s	178.788us	32	32	100.00
		pattgen_sec_cm	0.610s	5.396s	252.961us	3	3	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	0.940s	5.197s	178.788us	32	32	100.00
V2S		TOTAL				35	35	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	40.010s	43.085s	5.856ms	1	3	33.33
V3		TOTAL				1	3	33.33
	Unmapped tests	pattgen_inactive_level	14.780s	18.552s	10.067ms	4	5	80.00
		TOTAL				192	199	96.48

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	6	75.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.71	99.82	99.52	100.00	--	100.00	96.95	65.98

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

Job timed out after running for * minutes has 3 failures:
- Test pattgen_perf has 1 failures.
  - 2.pattgen_perf.39096985198799196530036422191538889574390944802486653035505412752713570800389
    Log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pattgen-sim-vcs/2.pattgen_perf/latest/run.log
```
  Job timed out after running for 60 minutes
```
- Test pattgen_stress_all has 2 failures.
  - 5.pattgen_stress_all.96282006733702103654066351523685109805082783343631912713364804373517853813793
    Log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pattgen-sim-vcs/5.pattgen_stress_all/latest/run.log
```
  Job timed out after running for 180 minutes
```
  - 6.pattgen_stress_all.54265417490878790151995067283028541478611542615828176365602491884282642328204
    Log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pattgen-sim-vcs/6.pattgen_stress_all/latest/run.log
```
  Job timed out after running for 180 minutes
```

UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

Test pattgen_stress_all_with_rand_reset has 2 failures.

1.pattgen_stress_all_with_rand_reset.53593393366370033172313113308457193918750800169954064121430871657497111255115
Line 156, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pattgen-sim-vcs/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2141562322 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2141570564 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2141570564 ps: (cip_base_vseq.sv:1154) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 2141631788 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.49664361873541443154740527358070921089256764136908808880050532260501433048218
Line 150, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pattgen-sim-vcs/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 576198055 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 576207405 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 576207405 ps: (cip_base_vseq.sv:1154) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 576238656 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 3.pattgen_inactive_level.49188786121059507730743844641916600872853577069165023404378637501219110986537
    Line 106, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pattgen-sim-vcs/3.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10067459344 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x535e450, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
  UVM_INFO @ 10067459344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 4.pattgen_stress_all.46779293301417486526218222473555432288277637727306942182350434681489073308966
    Line 190, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pattgen-sim-vcs/4.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 1372284010057 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  -----------------------------------
  Name      Type          Size  Value
  -----------------------------------
  exp_item  pattgen_item  -     @8080
```