| V1 |
prim_alert_request_test |
prim_async_alert |
0.320s |
5.551s |
11.482us |
4 |
4 |
100.00 |
|
|
prim_async_fatal_alert |
0.340s |
3.674s |
32.156us |
3 |
3 |
100.00 |
|
|
prim_sync_alert |
0.310s |
5.436s |
8.813us |
4 |
4 |
100.00 |
|
|
prim_sync_fatal_alert |
0.380s |
5.510s |
26.524us |
1 |
1 |
100.00 |
| V1 |
prim_alert_test |
prim_async_alert |
0.320s |
5.551s |
11.482us |
4 |
4 |
100.00 |
|
|
prim_async_fatal_alert |
0.340s |
3.674s |
32.156us |
3 |
3 |
100.00 |
|
|
prim_sync_alert |
0.310s |
5.436s |
8.813us |
4 |
4 |
100.00 |
|
|
prim_sync_fatal_alert |
0.380s |
5.510s |
26.524us |
1 |
1 |
100.00 |
| V1 |
prim_alert_ping_request_test |
prim_async_alert |
0.320s |
5.551s |
11.482us |
4 |
4 |
100.00 |
|
|
prim_async_fatal_alert |
0.340s |
3.674s |
32.156us |
3 |
3 |
100.00 |
|
|
prim_sync_alert |
0.310s |
5.436s |
8.813us |
4 |
4 |
100.00 |
|
|
prim_sync_fatal_alert |
0.380s |
5.510s |
26.524us |
1 |
1 |
100.00 |
| V1 |
prim_alert_integrity_errors_test |
prim_async_alert |
0.320s |
5.551s |
11.482us |
4 |
4 |
100.00 |
|
|
prim_async_fatal_alert |
0.340s |
3.674s |
32.156us |
3 |
3 |
100.00 |
|
|
prim_sync_alert |
0.310s |
5.436s |
8.813us |
4 |
4 |
100.00 |
|
|
prim_sync_fatal_alert |
0.380s |
5.510s |
26.524us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
|
12 |
12 |
100.00 |
| V2 |
prim_alert_init_trigger_test |
prim_async_alert |
0.320s |
5.551s |
11.482us |
4 |
4 |
100.00 |
|
|
prim_async_fatal_alert |
0.340s |
3.674s |
32.156us |
3 |
3 |
100.00 |
|
|
prim_sync_alert |
0.310s |
5.436s |
8.813us |
4 |
4 |
100.00 |
|
|
prim_sync_fatal_alert |
0.380s |
5.510s |
26.524us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
|
0 |
0 |
-- |
| V2S |
|
TOTAL |
|
|
|
0 |
0 |
-- |
| V3 |
prim_alert_gate_sender_clk_rst_test |
prim_alert_gate_sender_clk_rst_test |
|
|
|
0 |
0 |
-- |
| V3 |
|
TOTAL |
|
|
|
0 |
0 |
-- |
|
Unmapped tests |
prim_async_fatal_alert_with_3_cycles_skew |
0.380s |
5.541s |
30.306us |
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
|
15 |
15 |
100.00 |