PRIM_LFSR Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 TOTAL 0 0 --
V2 TOTAL 0 0 --
V2S TOTAL 0 0 --
V3 TOTAL 0 0 --
Unmapped tests prim_lfsr_fib_smoke 1.000s 6.429s 1.520ms 1 1 100.00
prim_lfsr_gal_smoke 1.030s 6.420s 1.532ms 3 3 100.00
prim_lfsr_gal_test 2.173m 7.747m 336.550ms 3 3 100.00
prim_lfsr_fib_test 2.251m 7.833m 336.911ms 3 3 100.00
TOTAL 10 10 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 4 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT
98.31 100.00 96.55 100.00 -- 100.00 95.00

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22