PWM/EGRET Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	1.450s	5.183s	513.200us	4	4	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	0.490s	5.009s	20.602us	5	5	100.00
V1	csr_rw	pwm_csr_rw	0.530s	5.001s	20.774us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	4.290s	7.812s	2.950ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	1.170s	5.029s	82.074us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	1.120s	5.017s	36.969us	5	5	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	0.530s	5.001s	20.774us	20	20	100.00
		pwm_csr_aliasing	1.170s	5.029s	82.074us	5	5	100.00
V1		TOTAL				44	44	100.00
V2	dutycycle	pwm_rand_output	32.230s	35.570s	10.718ms	10	10	100.00
V2	pulse	pwm_rand_output	32.230s	35.570s	10.718ms	10	10	100.00
V2	blink	pwm_rand_output	32.230s	35.570s	10.718ms	10	10	100.00
V2	heartbeat	pwm_rand_output	32.230s	35.570s	10.718ms	10	10	100.00
V2	resolution	pwm_rand_output	32.230s	35.570s	10.718ms	10	10	100.00
V2	multi_channel	pwm_rand_output	32.230s	35.570s	10.718ms	10	10	100.00
V2	polarity	pwm_rand_output	32.230s	35.570s	10.718ms	10	10	100.00
V2	phase	pwm_rand_output	32.230s	35.570s	10.718ms	10	10	100.00
		pwm_phase	27.210s	30.600s	10.509ms	8	8	100.00
V2	lowpower	pwm_rand_output	32.230s	35.570s	10.718ms	10	10	100.00
V2	perf	pwm_perf	20.540s	24.020s	65.614ms	3	3	100.00
V2	regwen	pwm_regwen	3.894m	3.965m	149.990ms	1	1	100.00
V2	stress_all	pwm_stress_all	1.980m	2.044m	107.238ms	20	20	100.00
V2	alert_test	pwm_alert_test	0.430s	4.337s	41.523us	3	3	100.00
V2	intr_test	pwm_intr_test				0	0	--
V2	tl_d_oob_addr_access	pwm_tl_errors	1.760s	5.332s	581.458us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	1.760s	5.332s	581.458us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	0.490s	5.009s	20.602us	5	5	100.00
		pwm_csr_rw	0.530s	5.001s	20.774us	20	20	100.00
		pwm_csr_aliasing	1.170s	5.029s	82.074us	5	5	100.00
		pwm_same_csr_outstanding	0.810s	4.962s	42.520us	3	3	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	0.490s	5.009s	20.602us	5	5	100.00
		pwm_csr_rw	0.530s	5.001s	20.774us	20	20	100.00
		pwm_csr_aliasing	1.170s	5.029s	82.074us	5	5	100.00
		pwm_same_csr_outstanding	0.810s	4.962s	42.520us	3	3	100.00
V2		TOTAL				68	68	100.00
V2S	tl_intg_err	pwm_tl_intg_err	1.500s	5.227s	236.990us	4	4	100.00
		pwm_sec_cm	0.680s	4.335s	250.549us	3	3	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	1.500s	5.227s	236.990us	4	4	100.00
V2S		TOTAL				7	7	100.00
V3	heartbeat_wrap	pwm_heartbeat_wrap	22.710s	26.432s	21.436ms	9	9	100.00
V3		TOTAL				9	9	100.00
		TOTAL				128	128	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	8	8	88.89
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.57	99.57	93.73	91.96	--	98.70	98.00	79.49

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22