PWRMGR/DRAGONFLY Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.470s	4.739s	27.576us	1	1	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.520s	4.545s	77.962us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.480s	4.488s	24.828us	3	3	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.120s	5.629s	321.770us	4	4	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.700s	4.562s	168.882us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	0.930s	4.774s	52.724us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.480s	4.488s	24.828us	3	3	100.00
		pwrmgr_csr_aliasing	0.700s	4.562s	168.882us	5	5	100.00
V1		TOTAL				38	38	100.00
V2	wakeup	pwrmgr_wakeup	0.550s	4.677s	58.647us	1	1	100.00
V2	control_clks	pwrmgr_wakeup	0.550s	4.677s	58.647us	1	1	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.600s	4.622s	125.218us	1	1	100.00
		pwrmgr_lowpower_invalid	0.550s	4.688s	101.270us	3	3	100.00
V2	reset	pwrmgr_reset	0.670s	4.728s	76.507us	2	3	66.67
		pwrmgr_reset_invalid	0.560s	4.631s	128.608us	2	3	66.67
V2	main_power_glitch_reset	pwrmgr_reset	0.670s	4.728s	76.507us	2	3	66.67
V2	reset_wakeup_race	pwrmgr_wakeup_reset	0.760s	4.649s	214.027us	1	1	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	0.760s	4.700s	365.845us	1	1	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.520s	4.597s	57.868us	1	3	33.33
V2	stress_all	pwrmgr_stress_all	3.870s	7.105s	1.863ms	4	4	100.00
V2	intr_test	pwrmgr_intr_test	0.470s	4.481s	43.354us	4	4	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	1.490s	5.591s	193.484us	4	4	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	1.490s	5.591s	193.484us	4	4	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.520s	4.545s	77.962us	5	5	100.00
		pwrmgr_csr_rw	0.480s	4.488s	24.828us	3	3	100.00
		pwrmgr_csr_aliasing	0.700s	4.562s	168.882us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.640s	4.758s	37.143us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.520s	4.545s	77.962us	5	5	100.00
		pwrmgr_csr_rw	0.480s	4.488s	24.828us	3	3	100.00
		pwrmgr_csr_aliasing	0.700s	4.562s	168.882us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.640s	4.758s	37.143us	20	20	100.00
V2		TOTAL				44	48	91.67
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.200s	4.938s	209.491us	20	20	100.00
		pwrmgr_sec_cm	1.400s	4.783s	641.539us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.400s	4.783s	641.539us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.400s	4.783s	641.539us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.200s	4.938s	209.491us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.460s	4.799s	1.020ms	6	6	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_wakeup_reset	0.760s	4.649s	214.027us	1	1	100.00
		pwrmgr_repeat_wakeup_reset				0	0	--
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.640s	4.757s	70.585us	1	1	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.420s	3.655s	29.351us	3	3	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.400s	4.783s	641.539us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.400s	4.783s	641.539us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.400s	4.783s	641.539us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.420s	3.653s	47.158us	1	1	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.480s	3.670s	62.199us	3	3	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	0.820s	4.780s	248.887us	3	3	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.480s	4.488s	24.828us	3	3	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.480s	4.488s	24.828us	3	3	100.00
V2S		TOTAL				42	42	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.530s	3.633s	153.052us	0	1	0.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	6.310s	9.619s	2.355ms	3	4	75.00
V3		TOTAL				3	5	60.00
		TOTAL				127	133	95.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	9	8	8	88.89
V3	2	2	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.42	99.24	96.57	96.87	96.00	97.19	97.22	70.84

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]' has 3 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 1.pwrmgr_reset_invalid.22491374130240168758259053917549120051836700312243450988346622825875348354796
      Line 154, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pwrmgr_top_dragonfly-sim-vcs/1.pwrmgr_reset_invalid/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @  35483218 ps: (pwrmgr_rstreqs_sva_if.sv:89) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @  35483218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_reset has 1 failures.

    • 2.pwrmgr_reset.46458255456527507510259616040658359550085263276895077247172944473310734873520
      Line 154, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pwrmgr_top_dragonfly-sim-vcs/2.pwrmgr_reset/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @  75516040 ps: (pwrmgr_rstreqs_sva_if.sv:89) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @  75516040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 3.pwrmgr_stress_all_with_rand_reset.20884008162855147296456433135065396958070715244902304839832579962842411256705
      Line 505, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pwrmgr_top_dragonfly-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 672496304 ps: (pwrmgr_rstreqs_sva_if.sv:89) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @ 672496304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_base_vseq.sv:584) [pwrmgr_disable_rom_integrity_check_vseq] timeout waiting for pwrmgr fast fsm target activity has 2 failures:

  • Test pwrmgr_disable_rom_integrity_check has 2 failures.

    • 1.pwrmgr_disable_rom_integrity_check.77465076019760740088853089513039636601333495700846049608761355053799383074165
      Line 87, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pwrmgr_top_dragonfly-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_FATAL @  82077123 ps: (pwrmgr_base_vseq.sv:584) [uvm_test_top.env.virtual_sequencer.pwrmgr_disable_rom_integrity_check_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @  82077123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.pwrmgr_disable_rom_integrity_check.5526921121847531638672621189935649631073651065883763345698622902286248949520
      Line 100, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pwrmgr_top_dragonfly-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_FATAL @  57868108 ps: (pwrmgr_base_vseq.sv:584) [uvm_test_top.env.virtual_sequencer.pwrmgr_disable_rom_integrity_check_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @  57868108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((!clk_en) || status)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 0.pwrmgr_escalation_timeout.16737804939062209263160648518563753137041810221651862271920694650099331578685
      Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pwrmgr_top_dragonfly-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log

            Offending '((!clk_en) || status)'
        UVM_ERROR @ 153052494 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
        UVM_INFO @ 153052494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---