PWRMGR/EGRET Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.480s	4.131s	40.676us	1	1	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.480s	4.493s	74.511us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.450s	4.362s	35.701us	3	3	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	1.730s	5.469s	268.590us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.670s	4.529s	54.375us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	0.870s	4.546s	52.191us	4	4	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.450s	4.362s	35.701us	3	3	100.00
		pwrmgr_csr_aliasing	0.670s	4.529s	54.375us	5	5	100.00
V1		TOTAL				23	23	100.00
V2	wakeup	pwrmgr_wakeup	0.650s	4.138s	415.983us	1	1	100.00
V2	control_clks	pwrmgr_wakeup	0.650s	4.138s	415.983us	1	1	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.560s	4.109s	36.092us	1	1	100.00
		pwrmgr_lowpower_invalid	0.490s	4.340s	83.221us	3	3	100.00
V2	reset	pwrmgr_reset	0.610s	4.145s	74.811us	1	1	100.00
		pwrmgr_reset_invalid	0.560s	4.312s	152.564us	2	3	66.67
V2	main_power_glitch_reset	pwrmgr_reset	0.610s	4.145s	74.811us	1	1	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	0.900s	4.118s	259.845us	1	1	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	0.430s	4.146s	45.265us	1	1	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.510s	4.262s	64.462us	1	1	100.00
V2	stress_all	pwrmgr_stress_all	1.420s	4.386s	444.495us	3	3	100.00
V2	intr_test	pwrmgr_intr_test	0.440s	4.500s	31.037us	4	4	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	1.340s	4.362s	485.113us	3	3	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	1.340s	4.362s	485.113us	3	3	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.480s	4.493s	74.511us	5	5	100.00
		pwrmgr_csr_rw	0.450s	4.362s	35.701us	3	3	100.00
		pwrmgr_csr_aliasing	0.670s	4.529s	54.375us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.670s	4.862s	48.084us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.480s	4.493s	74.511us	5	5	100.00
		pwrmgr_csr_rw	0.450s	4.362s	35.701us	3	3	100.00
		pwrmgr_csr_aliasing	0.670s	4.529s	54.375us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.670s	4.862s	48.084us	20	20	100.00
V2		TOTAL				41	42	97.62
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.150s	4.879s	277.448us	20	20	100.00
		pwrmgr_sec_cm	1.220s	4.394s	715.546us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.220s	4.394s	715.546us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.220s	4.394s	715.546us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.150s	4.879s	277.448us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.960s	5.439s	866.491us	4	4	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_wakeup_reset	0.900s	4.118s	259.845us	1	1	100.00
		pwrmgr_repeat_wakeup_reset				0	0	--
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.600s	4.152s	71.205us	1	1	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.450s	4.333s	30.556us	3	3	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.220s	4.394s	715.546us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.220s	4.394s	715.546us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.220s	4.394s	715.546us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.420s	4.192s	24.975us	1	1	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.450s	4.302s	61.061us	3	3	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	0.840s	4.315s	217.658us	3	3	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.450s	4.362s	35.701us	3	3	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.450s	4.362s	35.701us	3	3	100.00
V2S		TOTAL				40	40	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.510s	4.203s	386.133us	0	1	0.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	9.340s	13.070s	4.402ms	7	7	100.00
V3		TOTAL				7	8	87.50
		TOTAL				111	113	98.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	8	8	88.89
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.09	96.79	99.62	96.00	96.21	97.19	99.01

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• Offending '((!clk_en) || status)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 0.pwrmgr_escalation_timeout.92011550672416029403581094451563651222885526969664844615519766024685204403466
      Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pwrmgr_top_egret-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log

            Offending '((!clk_en) || status)'
        UVM_ERROR @ 386133236 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
        UVM_INFO @ 386133236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitDisClks has 1 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 2.pwrmgr_reset_invalid.31432028409142212179893452299698815406537301490873626259069897639236768887595
      Line 112, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/pwrmgr_top_egret-sim-vcs/2.pwrmgr_reset_invalid/latest/run.log

        UVM_FATAL @  26020962 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitDisClks
        UVM_INFO @  26020962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---