RACL_CTRL Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	racl_ctrl_smoke	0.530s	5.401s	23.353us	50	50	100.00
V1	csr_hw_reset	racl_ctrl_csr_hw_reset	0.490s	4.550s	27.626us	5	5	100.00
V1	csr_rw	racl_ctrl_csr_rw	0.520s	4.677s	40.409us	20	20	100.00
V1	csr_bit_bash	racl_ctrl_csr_bit_bash	1.890s	5.883s	783.987us	5	5	100.00
V1	csr_aliasing	racl_ctrl_csr_aliasing	0.540s	4.478s	69.804us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	racl_ctrl_csr_mem_rw_with_rand_reset	0.870s	4.797s	23.966us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	racl_ctrl_csr_rw	0.520s	4.677s	40.409us	20	20	100.00
		racl_ctrl_csr_aliasing	0.540s	4.478s	69.804us	5	5	100.00
V1		TOTAL				105	105	100.00
V2	error_log	error_log				0	0	--
V2	alert_test	racl_ctrl_alert_test	0.560s	5.410s	80.147us	50	50	100.00
V2	intr_test	racl_ctrl_intr_test	0.530s	4.969s	25.419us	50	50	100.00
V2	tl_d_oob_addr_access	racl_ctrl_tl_errors	1.780s	5.843s	262.881us	20	20	100.00
V2	tl_d_illegal_access	racl_ctrl_tl_errors	1.780s	5.843s	262.881us	20	20	100.00
V2	tl_d_outstanding_access	racl_ctrl_csr_hw_reset	0.490s	4.550s	27.626us	5	5	100.00
		racl_ctrl_csr_rw	0.520s	4.677s	40.409us	20	20	100.00
		racl_ctrl_csr_aliasing	0.540s	4.478s	69.804us	5	5	100.00
		racl_ctrl_same_csr_outstanding	0.650s	4.684s	75.160us	20	20	100.00
V2	tl_d_partial_access	racl_ctrl_csr_hw_reset	0.490s	4.550s	27.626us	5	5	100.00
		racl_ctrl_csr_rw	0.520s	4.677s	40.409us	20	20	100.00
		racl_ctrl_csr_aliasing	0.540s	4.478s	69.804us	5	5	100.00
		racl_ctrl_same_csr_outstanding	0.650s	4.684s	75.160us	20	20	100.00
V2		TOTAL				140	140	100.00
V2S	tl_intg_err	racl_ctrl_tl_intg_err	1.210s	5.048s	1.754ms	20	20	100.00
		racl_ctrl_sec_cm				0	0	--
V2S		TOTAL				20	20	100.00
V3	stress_all_with_rand_reset	racl_ctrl_stress_all_with_rand_reset	48.120s	51.096s	9.590ms	50	50	100.00
V3		TOTAL				50	50	100.00
	Unmapped tests	racl_ctrl_stress_all	1.960s	5.726s	2.654ms	50	50	100.00
		TOTAL				365	365	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	6	6	6	100.00
V2	5	4	4	80.00
V2S	2	1	1	50.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.91	98.93	88.45	99.41	--	96.68	96.07	77.91

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22