ROM_CTRL/32KB Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.790s	8.797s	186.983us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.290s	9.259s	312.459us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.270s	8.192s	1.859ms	3	3	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.590s	7.557s	302.174us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.500s	8.275s	549.098us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	5.050s	8.662s	555.385us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.270s	8.192s	1.859ms	3	3	100.00
		rom_ctrl_csr_aliasing	4.500s	8.275s	549.098us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.440s	7.599s	240.885us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.840s	7.178s	173.134us	5	5	100.00
V1		TOTAL				50	50	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	3.940s	7.724s	138.697us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	18.850s	21.886s	7.980ms	5	5	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.420s	10.792s	303.518us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	3.750s	7.188s	168.275us	3	3	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	6.970s	10.568s	210.862us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	6.970s	10.568s	210.862us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.290s	9.259s	312.459us	5	5	100.00
		rom_ctrl_csr_rw	4.270s	8.192s	1.859ms	3	3	100.00
		rom_ctrl_csr_aliasing	4.500s	8.275s	549.098us	5	5	100.00
		rom_ctrl_same_csr_outstanding	4.880s	8.599s	183.338us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.290s	9.259s	312.459us	5	5	100.00
		rom_ctrl_csr_rw	4.270s	8.192s	1.859ms	3	3	100.00
		rom_ctrl_csr_aliasing	4.500s	8.275s	549.098us	5	5	100.00
		rom_ctrl_same_csr_outstanding	4.880s	8.599s	183.338us	20	20	100.00
V2		TOTAL				52	52	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.368m	1.427m	9.551ms	4	4	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	15.720s	18.701s	2.186ms	3	3	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.275m	3.338m	1.187ms	3	3	100.00
		rom_ctrl_tl_intg_err	44.490s	48.288s	515.952us	5	5	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.275m	3.338m	1.187ms	3	3	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.275m	3.338m	1.187ms	3	3	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.368m	1.427m	9.551ms	4	4	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.368m	1.427m	9.551ms	4	4	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.368m	1.427m	9.551ms	4	4	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.368m	1.427m	9.551ms	4	4	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.368m	1.427m	9.551ms	4	4	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.275m	3.338m	1.187ms	3	3	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.275m	3.338m	1.187ms	3	3	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.790s	8.797s	186.983us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.790s	8.797s	186.983us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.790s	8.797s	186.983us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	44.490s	48.288s	515.952us	5	5	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.368m	1.427m	9.551ms	4	4	100.00
		rom_ctrl_kmac_err_chk	7.420s	10.792s	303.518us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.368m	1.427m	9.551ms	4	4	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.368m	1.427m	9.551ms	4	4	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.368m	1.427m	9.551ms	4	4	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	15.720s	18.701s	2.186ms	3	3	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.275m	3.338m	1.187ms	3	3	100.00
V2S		TOTAL				15	15	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	3.489m	3.551m	8.579ms	4	4	100.00
V3		TOTAL				4	4	100.00
		TOTAL				121	121	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.59	98.37	95.57	100.00	100.00	96.80	99.28

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22