ROM_CTRL/64KB Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.550s	11.504s	580.091us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.060s	14.575s	300.091us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.760s	10.564s	303.730us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.940s	10.508s	304.282us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.740s	9.374s	213.301us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.450s	11.418s	4.712ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.760s	10.564s	303.730us	20	20	100.00
		rom_ctrl_csr_aliasing	5.740s	9.374s	213.301us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.790s	10.466s	304.398us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.230s	10.256s	674.228us	5	5	100.00
V1		TOTAL				67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.720s	10.417s	221.397us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	31.280s	34.367s	3.767ms	4	4	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	18.040s	21.315s	14.140ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.430s	12.344s	1.999ms	3	3	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.720s	13.064s	4.143ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.720s	13.064s	4.143ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.060s	14.575s	300.091us	5	5	100.00
		rom_ctrl_csr_rw	6.760s	10.564s	303.730us	20	20	100.00
		rom_ctrl_csr_aliasing	5.740s	9.374s	213.301us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.810s	14.828s	1.036ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.060s	14.575s	300.091us	5	5	100.00
		rom_ctrl_csr_rw	6.760s	10.564s	303.730us	20	20	100.00
		rom_ctrl_csr_aliasing	5.740s	9.374s	213.301us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.810s	14.828s	1.036ms	20	20	100.00
V2		TOTAL				51	51	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.307m	2.362m	8.635ms	3	3	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	32.880s	36.493s	4.152ms	5	5	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	7.483m	7.545m	2.634ms	3	3	100.00
		rom_ctrl_tl_intg_err	1.548m	1.607m	432.823us	6	6	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	7.483m	7.545m	2.634ms	3	3	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	7.483m	7.545m	2.634ms	3	3	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.307m	2.362m	8.635ms	3	3	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.307m	2.362m	8.635ms	3	3	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.307m	2.362m	8.635ms	3	3	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.307m	2.362m	8.635ms	3	3	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.307m	2.362m	8.635ms	3	3	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	7.483m	7.545m	2.634ms	3	3	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	7.483m	7.545m	2.634ms	3	3	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.550s	11.504s	580.091us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.550s	11.504s	580.091us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.550s	11.504s	580.091us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.548m	1.607m	432.823us	6	6	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.307m	2.362m	8.635ms	3	3	100.00
		rom_ctrl_kmac_err_chk	18.040s	21.315s	14.140ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.307m	2.362m	8.635ms	3	3	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.307m	2.362m	8.635ms	3	3	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.307m	2.362m	8.635ms	3	3	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	32.880s	36.493s	4.152ms	5	5	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	7.483m	7.545m	2.634ms	3	3	100.00
V2S		TOTAL				17	17	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.827m	2.886m	6.791ms	5	5	100.00
V3		TOTAL				5	5	100.00
		TOTAL				140	140	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.59	98.37	95.57	100.00	100.00	96.80	99.28

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22