2aab100d17| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | TOTAL | 0 | 0 | -- | ||||
| V2 | TOTAL | 0 | 0 | -- | ||||
| V2S | unexpected_child_reset_activity | rstmgr_cnsty_chk_smoke | 0 | 0 | -- | |||
| V2S | child_reset_asserts_late | child_reset_asserts_late | 0 | 0 | -- | |||
| V2S | child_reset_releases_late | child_reset_releases_late | 0 | 0 | -- | |||
| V2S | parent_reset_asserts_late | parent_reset_asserts_late | 0 | 0 | -- | |||
| V2S | parent_reset_releases_late | parent_reset_releases_late | 0 | 0 | -- | |||
| V2S | TOTAL | 0 | 0 | -- | ||||
| V3 | TOTAL | 0 | 0 | -- | ||||
| Unmapped tests | rstmgr_cnsty_chk_test | 2.140s | 6.598s | 11.338ms | 8 | 10 | 80.00 | |
| TOTAL | 8 | 10 | 80.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V2S | 5 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
|---|---|---|---|---|---|---|
| 95.87 | 98.41 | 86.21 | 100.00 | 92.31 | 98.31 | 100.00 |
| Target | Elapsed |
|---|---|
| build | 00:06:40 |
| run | 14:15:03 |
| cov_merge | 14:15:15 |
| cov_report | 14:15:22 |
| Total | 14:15:22 |
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) has 2 failures:
6.rstmgr_cnsty_chk_test.106081012208012707601939535274075886517429059061480949129504266073494867444053
Line 175, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rstmgr_cnsty_chk_egret-sim-vcs/6.rstmgr_cnsty_chk_test/latest/run.log
UVM_ERROR @ 1798234720 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))
UVM_INFO @ 1816314720 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1834394720 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1852474720 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1870554720 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
7.rstmgr_cnsty_chk_test.82127975430323555070097458229441424481233217509583506393973690542598774283963
Line 175, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rstmgr_cnsty_chk_egret-sim-vcs/7.rstmgr_cnsty_chk_test/latest/run.log
UVM_ERROR @ 2020407462 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))
UVM_INFO @ 2040727462 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 2061047462 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 2081367462 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 2101687462 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16