RSTMGR/DRAGONFLY Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	0.940s	4.451s	73.800us	3	3	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.990s	5.294s	64.152us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.840s	5.284s	37.768us	3	3	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	3.570s	7.468s	196.612us	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.070s	5.309s	53.176us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.710s	5.280s	100.314us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.840s	5.284s	37.768us	3	3	100.00
		rstmgr_csr_aliasing	1.070s	5.309s	53.176us	5	5	100.00
V1		TOTAL				24	24	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.020s	4.454s	144.169us	3	3	100.00
V2	sw_rst	rstmgr_sw_rst	0.730s	4.445s	38.668us	3	3	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	0.820s	4.476s	78.682us	3	3	100.00
V2	reset_info	rstmgr_reset	3.730s	7.470s	538.453us	3	3	100.00
V2	cpu_info	rstmgr_reset	3.730s	7.470s	538.453us	3	3	100.00
V2	alert_info	rstmgr_reset	3.730s	7.470s	538.453us	3	3	100.00
V2	reset_info_capture	rstmgr_reset	3.730s	7.470s	538.453us	3	3	100.00
V2	stress_all	rstmgr_stress_all	21.130s	24.523s	3.203ms	5	5	100.00
V2	alert_test	rstmgr_alert_test	0.700s	4.448s	38.982us	3	3	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	1.860s	6.511s	47.996us	3	3	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	1.860s	6.511s	47.996us	3	3	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.990s	5.294s	64.152us	5	5	100.00
		rstmgr_csr_rw	0.840s	5.284s	37.768us	3	3	100.00
		rstmgr_csr_aliasing	1.070s	5.309s	53.176us	5	5	100.00
		rstmgr_same_csr_outstanding	0.950s	5.296s	75.221us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.990s	5.294s	64.152us	5	5	100.00
		rstmgr_csr_rw	0.840s	5.284s	37.768us	3	3	100.00
		rstmgr_csr_aliasing	1.070s	5.309s	53.176us	5	5	100.00
		rstmgr_same_csr_outstanding	0.950s	5.296s	75.221us	20	20	100.00
V2		TOTAL				43	43	100.00
V2S	tl_intg_err	rstmgr_sec_cm	14.770s	18.522s	3.393ms	3	3	100.00
		rstmgr_tl_intg_err	4.240s	7.579s	709.174us	6	6	100.00
V2S	prim_count_check	rstmgr_sec_cm	14.770s	18.522s	3.393ms	3	3	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	14.770s	18.522s	3.393ms	3	3	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	4.240s	7.579s	709.174us	6	6	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	0.830s	4.455s	60.048us	3	3	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	3.400s	6.602s	464.493us	5	5	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.740s	5.460s	291.485us	3	3	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	14.770s	18.522s	3.393ms	3	3	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.840s	5.284s	37.768us	3	3	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.840s	5.284s	37.768us	3	3	100.00
V2S		TOTAL				20	20	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset				0	0	--
V3		TOTAL				0	0	--
		TOTAL				87	87	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.19	99.43	100.00	--	99.72	97.62	98.49

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22