RSTMGR/EGRET Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	0.920s	4.549s	121.787us	1	1	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.710s	4.503s	151.983us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.630s	4.676s	84.901us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	6.650s	9.680s	2.297ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.320s	5.398s	167.206us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.170s	4.866s	178.996us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.630s	4.676s	84.901us	20	20	100.00
		rstmgr_csr_aliasing	1.320s	5.398s	167.206us	5	5	100.00
V1		TOTAL				56	56	100.00
V2	reset_stretcher	rstmgr_por_stretcher	0.610s	4.147s	175.992us	3	3	100.00
V2	sw_rst	rstmgr_sw_rst	1.770s	6.431s	492.952us	3	3	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	0.950s	4.372s	233.991us	3	3	100.00
V2	reset_info	rstmgr_reset	3.210s	6.454s	1.149ms	1	1	100.00
V2	cpu_info	rstmgr_reset	3.210s	6.454s	1.149ms	1	1	100.00
V2	alert_info	rstmgr_reset	3.210s	6.454s	1.149ms	1	1	100.00
V2	reset_info_capture	rstmgr_reset	3.210s	6.454s	1.149ms	1	1	100.00
V2	stress_all	rstmgr_stress_all	33.740s	37.000s	13.627ms	4	4	100.00
V2	alert_test	rstmgr_alert_test	0.580s	5.188s	80.821us	3	3	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	1.920s	5.543s	201.987us	4	4	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	1.920s	5.543s	201.987us	4	4	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.710s	4.503s	151.983us	5	5	100.00
		rstmgr_csr_rw	0.630s	4.676s	84.901us	20	20	100.00
		rstmgr_csr_aliasing	1.320s	5.398s	167.206us	5	5	100.00
		rstmgr_same_csr_outstanding	1.060s	4.348s	209.189us	3	3	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.710s	4.503s	151.983us	5	5	100.00
		rstmgr_csr_rw	0.630s	4.676s	84.901us	20	20	100.00
		rstmgr_csr_aliasing	1.320s	5.398s	167.206us	5	5	100.00
		rstmgr_same_csr_outstanding	1.060s	4.348s	209.189us	3	3	100.00
V2		TOTAL				24	24	100.00
V2S	tl_intg_err	rstmgr_sec_cm	22.320s	26.202s	16.832ms	3	3	100.00
		rstmgr_tl_intg_err	2.250s	6.306s	930.791us	6	6	100.00
V2S	prim_count_check	rstmgr_sec_cm	22.320s	26.202s	16.832ms	3	3	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	22.320s	26.202s	16.832ms	3	3	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	2.250s	6.306s	930.791us	6	6	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	0.810s	5.196s	181.816us	3	3	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	6.130s	9.419s	2.457ms	5	5	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	0.870s	5.265s	302.485us	3	3	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	22.320s	26.202s	16.832ms	3	3	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.630s	4.676s	84.901us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.630s	4.676s	84.901us	20	20	100.00
V2S		TOTAL				20	20	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset				0	0	--
V3		TOTAL				0	0	--
		TOTAL				100	100	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.51	99.38	100.00	--	99.83	98.13	98.76

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22