2aab100d17| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 3.930s | 7.772s | 2.061ms | 4 | 4 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.880s | 4.954s | 249.869us | 4 | 4 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.520s | 7.077s | 1.115ms | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 23.550s | 26.734s | 12.973ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 3.210s | 6.228s | 1.592ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 8.410s | 12.553s | 5.104ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 9.780s | 13.969s | 6.733ms | 3 | 3 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 56.870s | 1.012m | 56.140ms | 4 | 4 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 1.143m | 1.198m | 38.089ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.830s | 5.658s | 832.169us | 4 | 4 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.270s | 4.386s | 482.167us | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.020s | 4.435s | 344.120us | 4 | 4 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0.910s | 4.512s | 251.821us | 0 | 2 | 0.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.810s | 4.531s | 228.841us | 4 | 4 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.290s | 4.599s | 1.332ms | 4 | 4 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.720s | 4.640s | 152.742us | 4 | 4 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 3.270s | 6.500s | 1.431ms | 7 | 7 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 1.830s | 5.658s | 832.169us | 4 | 4 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.440s | 5.505s | 615.860us | 3 | 3 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 3.190s | 6.740s | 1.440ms | 5 | 5 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.020s | 4.435s | 344.120us | 4 | 4 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.600s | 4.553s | 213.486us | 3 | 3 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 1.900s | 6.565s | 430.596us | 4 | 4 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 1.580s | 6.343s | 182.898us | 3 | 3 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.012m | 1.084m | 81.223ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 46.460s | 49.824s | 34.042ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 2.470s | 6.603s | 102.821us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 46.460s | 49.824s | 34.042ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 1.580s | 6.343s | 182.898us | 3 | 3 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.610s | 5.278s | 47.545us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.630s | 5.280s | 103.525us | 4 | 4 | 100.00 |
| V1 | TOTAL | 141 | 143 | 98.60 | ||||
| V2 | idcode | rv_dm_smoke | 3.930s | 7.772s | 2.061ms | 4 | 4 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 0.940s | 4.576s | 741.669us | 4 | 4 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.580s | 4.636s | 666.716us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 0.810s | 4.535s | 731.273us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.620s | 5.728s | 1.123ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 8.801m | 8.854m | 300.000ms | 0 | 20 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 8.904m | 8.961m | 300.000ms | 0 | 20 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 9.442m | 9.504m | 300.000ms | 0 | 20 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 8.516m | 8.581m | 300.000ms | 0 | 20 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.720s | 4.598s | 436.700us | 0 | 2 | 0.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 4.090s | 8.016s | 2.240ms | 5 | 5 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0.690s | 4.654s | 185.194us | 4 | 4 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.820s | 4.525s | 188.553us | 0 | 5 | 0.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 13.210s | 17.659s | 9.311ms | 4 | 4 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 1.233m | 1.303m | 36.641ms | 8 | 8 | 100.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 0.920s | 4.592s | 263.902us | 4 | 4 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 2.531h | 2.533h | 10.000s | 3 | 7 | 42.86 |
| V2 | alert_test | rv_dm_alert_test | 0.720s | 4.571s | 140.353us | 4 | 4 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 4.180s | 8.450s | 638.125us | 4 | 4 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 4.180s | 8.450s | 638.125us | 4 | 4 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 46.460s | 49.824s | 34.042ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 1.900s | 6.565s | 430.596us | 4 | 4 | 100.00 | ||
| rv_dm_csr_rw | 1.580s | 6.343s | 182.898us | 3 | 3 | 100.00 | ||
| rv_dm_same_csr_outstanding | 2.970s | 6.517s | 570.974us | 3 | 3 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 46.460s | 49.824s | 34.042ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 1.900s | 6.565s | 430.596us | 4 | 4 | 100.00 | ||
| rv_dm_csr_rw | 1.580s | 6.343s | 182.898us | 3 | 3 | 100.00 | ||
| rv_dm_same_csr_outstanding | 2.970s | 6.517s | 570.974us | 3 | 3 | 100.00 | ||
| V2 | TOTAL | 49 | 140 | 35.00 | ||||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.250s | 5.631s | 2.247ms | 4 | 4 | 100.00 |
| rv_dm_tl_intg_err | 23.470s | 27.308s | 6.891ms | 11 | 11 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 23.470s | 27.308s | 6.891ms | 11 | 11 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 4.090s | 8.016s | 2.240ms | 5 | 5 | 100.00 |
| rv_dm_debug_disabled | 0.590s | 4.565s | 69.568us | 2 | 3 | 66.67 | ||
| V2S | sec_cm_lc_hw_debug_clr_intersig_mubi | sec_cm_lc_hw_debug_clr_intersig_mubi | 0 | 0 | -- | |||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 4.090s | 8.016s | 2.240ms | 5 | 5 | 100.00 |
| rv_dm_debug_disabled | 0.590s | 4.565s | 69.568us | 2 | 3 | 66.67 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 3.930s | 7.772s | 2.061ms | 4 | 4 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 1.100s | 4.580s | 674.294us | 5 | 5 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.930s | 4.581s | 279.702us | 4 | 4 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.930s | 4.581s | 279.702us | 4 | 4 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 1.100s | 4.580s | 674.294us | 5 | 5 | 100.00 |
| V2S | TOTAL | 26 | 27 | 96.30 | ||||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 43.900s | 47.494s | 9.998ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | ||||
| Unmapped tests | rv_dm_scanmode | 2.381m | 2.435m | 300.000ms | 0 | 1 | 0.00 | |
| TOTAL | 216 | 321 | 67.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 27 | 27 | 26 | 96.30 |
| V2 | 19 | 19 | 12 | 63.16 |
| V2S | 6 | 5 | 4 | 66.67 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 76.22 | 89.95 | 77.76 | 69.97 | 39.47 | 74.68 | 96.24 | 85.46 |
| Target | Elapsed |
|---|---|
| build | 00:06:40 |
| run | 14:15:03 |
| cov_merge | 14:15:15 |
| cov_report | 14:15:22 |
| Total | 14:15:22 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 83 failures:
Test rv_dm_sba_tl_access has 20 failures.
0.rv_dm_sba_tl_access.102172392745054438413669407224674972522767384852182813015566916284906848387857
Line 90, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_sba_tl_access.21319761675730444900398934738930523628028009124681781876629861825076086098825
Line 90, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_delayed_resp_sba_tl_access has 20 failures.
0.rv_dm_delayed_resp_sba_tl_access.91806096824965698329361131456214726825279427988734044561887464343869416899304
Line 90, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_delayed_resp_sba_tl_access.86418963364988461164371884154822668368732502730264841513049846859376491186039
Line 90, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_bad_sba_tl_access has 20 failures.
0.rv_dm_bad_sba_tl_access.12328301107502255743742233108660667283307497896729235588672701332802541477343
Line 90, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_bad_sba_tl_access.99300266669276172395457522651916173401476893522113578201309016290060397403845
Line 90, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_autoincr_sba_tl_access has 20 failures.
0.rv_dm_autoincr_sba_tl_access.17219649627728486151591035192579924214874417468663934920063659707400521056103
Line 90, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_autoincr_sba_tl_access.107029789904329896049863883720225792439964025241589514107532626368814712913279
Line 90, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_scanmode has 1 failures.
0.rv_dm_scanmode.5689858706962576398169639921327395335690288594301913519589969753015609726518
Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_scanmode/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 7 failures:
0.rv_dm_hart_unavail.5082113559704126243755530368760760871301010637451158228436410052640372237832
Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 42442306 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 42442306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_hart_unavail.98369823671882182068271610533338243008349867159601357524263491360564625651499
Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 76076880 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 76076880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
0.rv_dm_stress_all_with_rand_reset.45841933599095709457703950061196618853489135035744681699091319827299356265564
Line 100, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 953717097 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 953717097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_stress_all_with_rand_reset.52022960674590420022091646707890118026678284409307051670226335102365988788585
Line 117, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1979718168 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1979718168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 6 failures:
Test rv_dm_jtag_dmi_debug_disabled has 2 failures.
0.rv_dm_jtag_dmi_debug_disabled.33194961547358619329612437195709294162628022959114571884826239966109558239432
Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 436700310 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1311283240 [0x4e289828] vs 0 [0x0])
UVM_INFO @ 436700310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dmi_debug_disabled.1476290302553086747596753832668034087219256089279581567627896076507491927981
Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 270034823 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1563461061 [0x5d3085c5] vs 0 [0x0])
UVM_INFO @ 270034823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
1.rv_dm_stress_all_with_rand_reset.57806516427750292410806090172774189398357203484646122387615161214918904125966
Line 84, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 261006412 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3354704430 [0xc7f4ba2e] vs 0 [0x0])
UVM_INFO @ 261006412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_stress_all_with_rand_reset.47767524549306736319418779939911932497323434815952494152805478972999479197944
Line 84, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 204520608 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1942032772 [0x73c11184] vs 0 [0x0])
UVM_INFO @ 204520608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 2 failures.
3.rv_dm_stress_all.45434908863802239777387877764570600457456785083888452414921214927508291621454
Line 82, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 226532524 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3014212866 [0xb3a93d02] vs 0 [0x0])
UVM_INFO @ 226532524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_stress_all.59229481906588559788430080568519628952669418904927759722167977197312609902616
Line 82, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 447614111 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1656081720 [0x62b5cd38] vs 0 [0x0])
UVM_INFO @ 447614111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 4 failures:
Test rv_dm_mem_tl_access_resuming has 2 failures.
0.rv_dm_mem_tl_access_resuming.15254513879060351303122046705954898798218115813310389965140991906132795082636
Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 81825373 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 81825373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_mem_tl_access_resuming.70063965012204231750953859267665831113368741751584426857473583518555112815381
Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 251821053 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 251821053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
6.rv_dm_stress_all_with_rand_reset.23079363416503085902046891515623248421551993494137363479305443154497506387747
Line 90, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2048598607 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2048598607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all_with_rand_reset.31332639448637674205454069096760410501859033071706195463423040075546087163697
Line 84, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 144960251 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 144960251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1171) [rv_dm_common_vseq] Check failed (vseq_done) has 4 failures:
2.rv_dm_stress_all_with_rand_reset.80922931780893441930033564838147597542587016136785574015001133160418174572484
Line 90, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3415953318 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 3415953318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_stress_all_with_rand_reset.59852248046586238293448038866268987922592961629217063902093858400729274201606
Line 165, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2997266698 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2997266698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) has 1 failures:
2.rv_dm_debug_disabled.753688781515721638708267341732389618780601357644780641708335056600993437488
Line 83, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_dm_use_dmi_interface-sim-vcs/2.rv_dm_debug_disabled/latest/run.log
UVM_ERROR @ 20086897 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
UVM_INFO @ 20086897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---