RV_DM/USE_JTAG_INTERFACE Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 4.800s 8.542s 2.628ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.310s 5.227s 536.131us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.540s 5.382s 718.299us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 43.410s 46.707s 27.315ms 3 3 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.220s 5.184s 538.893us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 9.840s 14.861s 19.031ms 7 7 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 11.470s 15.103s 6.275ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 40.150s 43.571s 26.818ms 3 3 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.258m 3.325m 217.228ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 0.970s 4.209s 314.614us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.790s 4.199s 853.919us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.300s 5.145s 1.076ms 3 3 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 0.580s 4.258s 186.353us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.630s 4.263s 195.884us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 0.900s 4.281s 999.703us 3 3 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.650s 4.250s 101.154us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.840s 6.029s 1.382ms 8 8 100.00
V1 progbuf_busy rv_dm_cmderr_busy 0.970s 4.209s 314.614us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.130s 4.409s 359.053us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.870s 4.476s 228.660us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.300s 5.145s 1.076ms 3 3 100.00
V1 rom_read_access rv_dm_rom_read_access 0.660s 4.500s 172.007us 3 3 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 1.590s 6.096s 169.654us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 1.730s 5.224s 190.198us 3 3 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 48.720s 52.152s 33.228ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 42.280s 45.599s 4.532ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 2.750s 6.414s 244.196us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 42.280s 45.599s 4.532ms 5 5 100.00
rv_dm_csr_rw 1.730s 5.224s 190.198us 3 3 100.00
V1 mem_walk rv_dm_mem_walk 0.620s 4.152s 133.659us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.680s 4.312s 133.718us 5 5 100.00
V1 TOTAL 149 149 100.00
V2 idcode rv_dm_smoke 4.800s 8.542s 2.628ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 0.720s 4.395s 134.572us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.760s 4.318s 690.887us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 0.670s 4.460s 117.298us 3 3 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0.900s 4.292s 286.587us 2 2 100.00
V2 sba rv_dm_sba_tl_access 8.270m 8.340m 300.000ms 0 20 0.00
rv_dm_delayed_resp_sba_tl_access 8.992m 9.044m 300.000ms 0 20 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 8.197m 8.254m 300.000ms 0 20 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 8.825m 8.888m 300.000ms 0 20 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.750s 4.421s 315.519us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 3.950s 7.613s 2.036ms 5 5 100.00
V2 ndmreset_req rv_dm_ndmreset_req 0.730s 4.318s 526.432us 3 3 100.00
V2 hart_unavail rv_dm_hart_unavail 0.850s 4.239s 340.558us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 13.590s 16.689s 9.602ms 3 3 100.00
rv_dm_tap_fsm_rand_reset 1.230m 1.285m 8.994ms 8 8 100.00
V2 hartsel_warl rv_dm_hartsel_warl 0.510s 4.441s 108.130us 1 1 100.00
V2 stress_all rv_dm_stress_all 8.740s 13.080s 4.323ms 14 14 100.00
V2 alert_test rv_dm_alert_test 0.510s 4.262s 47.035us 3 3 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 3.740s 7.616s 1.089ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 3.740s 7.616s 1.089ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 42.280s 45.599s 4.532ms 5 5 100.00
rv_dm_csr_hw_reset 1.590s 6.096s 169.654us 5 5 100.00
rv_dm_csr_rw 1.730s 5.224s 190.198us 3 3 100.00
rv_dm_same_csr_outstanding 2.920s 7.297s 302.785us 3 3 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 42.280s 45.599s 4.532ms 5 5 100.00
rv_dm_csr_hw_reset 1.590s 6.096s 169.654us 5 5 100.00
rv_dm_csr_rw 1.730s 5.224s 190.198us 3 3 100.00
rv_dm_same_csr_outstanding 2.920s 7.297s 302.785us 3 3 100.00
V2 TOTAL 76 156 48.72
V2S tl_intg_err rv_dm_sec_cm 3.220s 6.364s 2.710ms 5 5 100.00
rv_dm_tl_intg_err 18.330s 21.974s 5.385ms 11 11 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 18.330s 21.974s 5.385ms 11 11 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 3.950s 7.613s 2.036ms 5 5 100.00
rv_dm_debug_disabled 0.660s 4.495s 67.161us 2 2 100.00
V2S sec_cm_lc_hw_debug_clr_intersig_mubi sec_cm_lc_hw_debug_clr_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 3.950s 7.613s 2.036ms 5 5 100.00
rv_dm_debug_disabled 0.660s 4.495s 67.161us 2 2 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 4.800s 8.542s 2.628ms 2 2 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.620s 5.301s 626.299us 5 5 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 0.750s 4.280s 207.768us 5 5 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 0.750s 4.280s 207.768us 5 5 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.620s 5.301s 626.299us 5 5 100.00
V2S TOTAL 28 28 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.458m 1.515m 5.433ms 9 9 100.00
V3 TOTAL 9 9 100.00
Unmapped tests rv_dm_scanmode 0.480s 4.247s 26.334us 1 1 100.00
TOTAL 263 343 76.68

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 27 27 27 100.00
V2 19 19 15 78.95
V2S 6 5 5 83.33
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
81.85 95.49 89.66 71.98 87.80 87.86 95.31 44.86

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22

Failure Buckets