2aab100d17| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 1.920s | 6.199s | 212.498us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.430s | 4.330s | 34.294us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.430s | 4.375s | 31.231us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.430s | 6.165s | 2.282ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.580s | 4.350s | 259.469us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.060s | 4.428s | 62.351us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.430s | 4.375s | 31.231us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.580s | 4.350s | 259.469us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 56 | 56 | 100.00 | ||||
| V2 | random_reset | rv_timer_random_reset | 1.040s | 4.094s | 435.997us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 0.620s | 4.140s | 1.570ms | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 6.150m | 6.207m | 1.324s | 3 | 3 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 6.150m | 6.207m | 1.324s | 3 | 3 | 100.00 |
| V2 | stress | rv_timer_stress_all | 0.740s | 4.062s | 1.410ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.400s | 4.116s | 13.983us | 3 | 3 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.420s | 4.388s | 161.675us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.030s | 6.197s | 153.390us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.030s | 6.197s | 153.390us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.430s | 4.330s | 34.294us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.430s | 4.375s | 31.231us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.580s | 4.350s | 259.469us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.570s | 4.223s | 46.254us | 3 | 3 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.430s | 4.330s | 34.294us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.430s | 4.375s | 31.231us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.580s | 4.350s | 259.469us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.570s | 4.223s | 46.254us | 3 | 3 | 100.00 | ||
| V2 | TOTAL | 81 | 82 | 98.78 | ||||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.680s | 4.129s | 577.794us | 3 | 3 | 100.00 |
| rv_timer_tl_intg_err | 0.950s | 4.217s | 239.666us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.950s | 4.217s | 239.666us | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | ||||
| V3 | min_value | rv_timer_min | 1.180s | 8.149s | 654.355us | 1 | 4 | 25.00 |
| V3 | max_value | rv_timer_max | 0.460s | 7.136s | 178.003us | 1 | 4 | 25.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 34.930s | 38.077s | 8.807ms | 4 | 5 | 80.00 |
| V3 | TOTAL | 6 | 13 | 46.15 | ||||
| TOTAL | 149 | 157 | 94.90 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 7 | 87.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.47 | 100.00 | 100.00 | 100.00 | -- | 100.00 | 96.82 | 100.00 |
| Target | Elapsed |
|---|---|
| build | 00:06:40 |
| run | 14:15:03 |
| cov_merge | 14:15:15 |
| cov_report | 14:15:22 |
| Total | 14:15:22 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 4 failures:
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.105750327487476927788097661138249964067318922786986341854840800846095776513029
Line 77, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 435997379 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7d64a104) == 0x1
UVM_INFO @ 435997379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_min has 3 failures.
1.rv_timer_min.3768120970684880475090273315653608425589509279210830424810995841605969570506
Line 77, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
UVM_FATAL @ 654354702 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x443d5904) == 0x1
UVM_INFO @ 654354702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_min.941176391278258075324923902651388190989617369757848054831960954675721660291
Line 77, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_timer-sim-vcs/2.rv_timer_min/latest/run.log
UVM_FATAL @ 250849034 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xdddb0904) == 0x1
UVM_INFO @ 250849034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 3 failures:
1.rv_timer_max.57363345379378912423016340781546506630891128156016484896473174806774937258741
Line 77, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
UVM_ERROR @ 182746444 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 182746444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_max.6841791541347807150503701642504996631721178030899405293346858473687346793513
Line 78, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_timer-sim-vcs/2.rv_timer_max/latest/run.log
UVM_ERROR @ 178002830 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 178002830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
3.rv_timer_stress_all_with_rand_reset.108559813973237098940879200499648287304740015665565393170185418352905994257806
Line 87, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16776570 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 16776570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---