SPI_DEVICE/1R1W Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 9.600s 14.204s 1.466ms 0 6 0.00
V1 csr_hw_reset spi_device_csr_hw_reset 0.940s 4.809s 226.079us 3 3 100.00
V1 csr_rw spi_device_csr_rw 1.600s 4.845s 247.791us 3 3 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 22.120s 25.734s 1.864ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 5.820s 9.209s 1.745ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.690s 6.162s 245.204us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.600s 4.845s 247.791us 3 3 100.00
spi_device_csr_aliasing 5.820s 9.209s 1.745ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.490s 4.493s 37.808us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.410s 5.344s 93.346us 5 5 100.00
V1 TOTAL 46 52 88.46
V2 csb_read spi_device_csb_read 0.580s 4.637s 80.252us 1 1 100.00
V2 mem_parity spi_device_mem_parity 0.570s 4.721s 1.374us 0 20 0.00
V2 mem_cfg spi_device_ram_cfg 0.500s 3.592s 6.714us 0 1 0.00
V2 tpm_read spi_device_tpm_rw 0.910s 4.703s 29.994us 0 1 0.00
V2 tpm_write spi_device_tpm_rw 0.910s 4.703s 29.994us 0 1 0.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 3.210s 7.668s 2.512ms 3 3 100.00
spi_device_tpm_sts_read 0.530s 4.712s 124.084us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 0.500s 3.583s 12.259us 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 9.980s 13.136s 27.692ms 3 3 100.00
spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 12.910s 17.648s 7.859ms 3 3 100.00
spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 12.910s 17.648s 7.859ms 3 3 100.00
spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 cmd_info_slots spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 cmd_read_status spi_device_intercept 11.480s 16.671s 7.147ms 3 3 100.00
spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 cmd_read_jedec spi_device_intercept 11.480s 16.671s 7.147ms 3 3 100.00
spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 cmd_read_sfdp spi_device_intercept 11.480s 16.671s 7.147ms 3 3 100.00
spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 cmd_fast_read spi_device_intercept 11.480s 16.671s 7.147ms 3 3 100.00
spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 cmd_read_pipeline spi_device_intercept 11.480s 16.671s 7.147ms 3 3 100.00
spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 flash_cmd_upload spi_device_upload 1.740s 5.692s 328.484us 1 1 100.00
V2 mailbox_command spi_device_mailbox 13.970s 17.472s 1.486ms 3 3 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 13.970s 17.472s 1.486ms 3 3 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 13.970s 17.472s 1.486ms 3 3 100.00
V2 cmd_read_buffer spi_device_flash_mode 12.780s 17.763s 5.179ms 0 5 0.00
spi_device_read_buffer_direct 2.580s 5.698s 503.994us 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 13.970s 17.472s 1.486ms 3 3 100.00
spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 quad_spi spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 dual_spi spi_device_flash_all 42.650s 46.006s 12.148ms 0 6 0.00
V2 4b_3b_feature spi_device_cfg_cmd 1.550s 4.555s 155.657us 0 1 0.00
V2 write_enable_disable spi_device_cfg_cmd 1.550s 4.555s 155.657us 0 1 0.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 9.600s 14.204s 1.466ms 0 6 0.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 1.214m 1.270m 80.462ms 0 6 0.00
V2 stress_all spi_device_stress_all 9.500s 13.102s 8.653ms 0 14 0.00
V2 alert_test spi_device_alert_test 0.510s 4.477s 31.200us 3 3 100.00
V2 intr_test spi_device_intr_test 0.550s 4.802s 49.151us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.520s 6.548s 815.865us 5 5 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.520s 6.548s 815.865us 5 5 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 0.940s 4.809s 226.079us 3 3 100.00
spi_device_csr_rw 1.600s 4.845s 247.791us 3 3 100.00
spi_device_csr_aliasing 5.820s 9.209s 1.745ms 5 5 100.00
spi_device_same_csr_outstanding 2.940s 6.608s 210.921us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 0.940s 4.809s 226.079us 3 3 100.00
spi_device_csr_rw 1.600s 4.845s 247.791us 3 3 100.00
spi_device_csr_aliasing 5.820s 9.209s 1.745ms 5 5 100.00
spi_device_same_csr_outstanding 2.940s 6.608s 210.921us 20 20 100.00
V2 TOTAL 98 152 64.47
V2S tl_intg_err spi_device_sec_cm 0.870s 5.451s 1.733ms 3 3 100.00
spi_device_tl_intg_err 15.950s 19.145s 2.207ms 5 5 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 15.950s 19.145s 2.207ms 5 5 100.00
V2S TOTAL 8 8 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_device_flash_mode_ignore_cmds 1.020m 1.086m 17.406ms 0 8 0.00
TOTAL 152 220 69.09

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 22 22 14 63.64
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
74.08 95.80 90.84 70.75 59.57 95.14 87.16 19.30

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22

Failure Buckets