SPI_DEVICE/2P Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 3.220s 6.745s 1.303ms 0 12 0.00
V1 csr_hw_reset spi_device_csr_hw_reset 0.960s 4.524s 44.795us 3 3 100.00
V1 csr_rw spi_device_csr_rw 1.730s 5.391s 583.751us 3 3 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 24.020s 27.736s 1.803ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 14.860s 18.561s 3.751ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.580s 6.343s 377.867us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.730s 5.391s 583.751us 3 3 100.00
spi_device_csr_aliasing 14.860s 18.561s 3.751ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.480s 4.381s 23.006us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.510s 5.408s 64.038us 5 5 100.00
V1 TOTAL 46 58 79.31
V2 csb_read spi_device_csb_read 0.680s 5.208s 18.891us 1 1 100.00
V2 mem_parity spi_device_mem_parity 0.730s 4.250s 31.685us 3 3 100.00
V2 mem_cfg spi_device_ram_cfg 0.520s 4.252s 16.776us 4 4 100.00
V2 tpm_read spi_device_tpm_rw 0.470s 4.114s 30.221us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 0.470s 4.114s 30.221us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 4.330s 8.256s 4.387ms 1 1 100.00
spi_device_tpm_sts_read 0.540s 4.325s 68.218us 3 3 100.00
V2 tpm_fully_random_case spi_device_tpm_all 1.340s 5.139s 369.709us 0 4 0.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 7.160s 10.152s 21.083ms 1 1 100.00
spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 12.220s 15.282s 16.108ms 3 3 100.00
spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 12.220s 15.282s 16.108ms 3 3 100.00
spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 cmd_info_slots spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 cmd_read_status spi_device_intercept 2.270s 6.046s 514.499us 1 1 100.00
spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 cmd_read_jedec spi_device_intercept 2.270s 6.046s 514.499us 1 1 100.00
spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 cmd_read_sfdp spi_device_intercept 2.270s 6.046s 514.499us 1 1 100.00
spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 cmd_fast_read spi_device_intercept 2.270s 6.046s 514.499us 1 1 100.00
spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 cmd_read_pipeline spi_device_intercept 2.270s 6.046s 514.499us 1 1 100.00
spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 flash_cmd_upload spi_device_upload 3.670s 7.142s 2.585ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 1.809m 1.873m 75.788ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 1.809m 1.873m 75.788ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 1.809m 1.873m 75.788ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 35.040s 38.841s 10.510ms 0 5 0.00
spi_device_read_buffer_direct 5.430s 9.067s 4.136ms 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 1.809m 1.873m 75.788ms 1 1 100.00
spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 quad_spi spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 dual_spi spi_device_flash_all 1.123m 1.187m 77.708ms 0 6 0.00
V2 4b_3b_feature spi_device_cfg_cmd 2.730s 6.161s 266.622us 0 3 0.00
V2 write_enable_disable spi_device_cfg_cmd 2.730s 6.161s 266.622us 0 3 0.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 3.220s 6.745s 1.303ms 0 12 0.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 6.740s 10.754s 3.064ms 0 7 0.00
V2 stress_all spi_device_stress_all 3.200s 6.779s 3.666ms 0 9 0.00
V2 alert_test spi_device_alert_test 0.490s 4.330s 21.649us 3 3 100.00
V2 intr_test spi_device_intr_test 0.570s 4.892s 27.309us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.660s 7.664s 410.625us 6 6 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.660s 7.664s 410.625us 6 6 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 0.960s 4.524s 44.795us 3 3 100.00
spi_device_csr_rw 1.730s 5.391s 583.751us 3 3 100.00
spi_device_csr_aliasing 14.860s 18.561s 3.751ms 5 5 100.00
spi_device_same_csr_outstanding 2.950s 6.625s 223.062us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 0.960s 4.524s 44.795us 3 3 100.00
spi_device_csr_rw 1.730s 5.391s 583.751us 3 3 100.00
spi_device_csr_aliasing 14.860s 18.561s 3.751ms 5 5 100.00
spi_device_same_csr_outstanding 2.950s 6.625s 223.062us 20 20 100.00
V2 TOTAL 100 134 74.63
V2S tl_intg_err spi_device_sec_cm 0.980s 4.390s 961.875us 3 3 100.00
spi_device_tl_intg_err 13.860s 17.603s 915.108us 5 5 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 13.860s 17.603s 915.108us 5 5 100.00
V2S TOTAL 8 8 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_device_flash_mode_ignore_cmds 24.940s 28.455s 25.877ms 0 8 0.00
TOTAL 154 208 74.04

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 22 22 16 72.73
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
74.49 96.23 91.88 72.91 57.45 95.56 88.11 19.30

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22

Failure Buckets