SPI_HOST Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 20.260s 23.333s 696.893us 0 8 0.00
V1 csr_hw_reset spi_host_csr_hw_reset 0.470s 4.169s 68.882us 5 5 100.00
V1 csr_rw spi_host_csr_rw 0.510s 4.982s 22.107us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 1.740s 5.412s 1.067ms 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 0.570s 4.146s 29.756us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 0.750s 4.157s 41.415us 4 4 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 0.510s 4.982s 22.107us 20 20 100.00
spi_host_csr_aliasing 0.570s 4.146s 29.756us 5 5 100.00
V1 mem_walk spi_host_mem_walk 0.470s 4.175s 34.901us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 0.520s 4.164s 71.030us 5 5 100.00
V1 TOTAL 49 57 85.96
V2 performance spi_host_performance 0.820s 4.169s 37.932us 0 4 0.00
V2 error_event_intr spi_host_overflow_underflow 1.610s 5.287s 124.761us 3 3 100.00
spi_host_error_cmd 0.460s 4.227s 46.706us 3 3 100.00
spi_host_event 28.310s 31.676s 1.144ms 1 1 100.00
V2 clock_rate spi_host_speed 1.690s 5.165s 63.546us 0 8 0.00
V2 speed spi_host_speed 1.690s 5.165s 63.546us 0 8 0.00
V2 chip_select_timing spi_host_speed 1.690s 5.165s 63.546us 0 8 0.00
V2 sw_reset spi_host_sw_reset 3.260s 7.089s 82.338us 0 8 0.00
V2 passthrough_mode spi_host_passthrough_mode 0.440s 4.227s 27.537us 4 4 100.00
V2 cpol_cpha spi_host_speed 1.690s 5.165s 63.546us 0 8 0.00
V2 full_cycle spi_host_speed 1.690s 5.165s 63.546us 0 8 0.00
V2 duplex spi_host_smoke 20.260s 23.333s 696.893us 0 8 0.00
V2 tx_rx_only spi_host_smoke 20.260s 23.333s 696.893us 0 8 0.00
V2 stress_all spi_host_stress_all 14.320s 17.306s 488.076us 0 15 0.00
V2 spien spi_host_spien 1.000s 4.163s 20.839us 0 5 0.00
V2 stall spi_host_status_stall 3.766m 3.829m 26.837ms 0 13 0.00
V2 Idlecsbactive spi_host_idlecsbactive 0.720s 4.149s 42.524us 0 1 0.00
V2 data_fifo_status spi_host_overflow_underflow 1.610s 5.287s 124.761us 3 3 100.00
V2 alert_test spi_host_alert_test 0.430s 4.239s 29.893us 3 3 100.00
V2 intr_test spi_host_intr_test 0.480s 4.137s 24.970us 4 4 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 2.130s 5.617s 571.651us 4 4 100.00
V2 tl_d_illegal_access spi_host_tl_errors 2.130s 5.617s 571.651us 4 4 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 0.470s 4.169s 68.882us 5 5 100.00
spi_host_csr_rw 0.510s 4.982s 22.107us 20 20 100.00
spi_host_csr_aliasing 0.570s 4.146s 29.756us 5 5 100.00
spi_host_same_csr_outstanding 0.610s 5.081s 28.388us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 0.470s 4.169s 68.882us 5 5 100.00
spi_host_csr_rw 0.510s 4.982s 22.107us 20 20 100.00
spi_host_csr_aliasing 0.570s 4.146s 29.756us 5 5 100.00
spi_host_same_csr_outstanding 0.610s 5.081s 28.388us 20 20 100.00
V2 TOTAL 42 96 43.75
V2S tl_intg_err spi_host_tl_intg_err 1.020s 5.456s 100.473us 6 6 100.00
spi_host_sec_cm 0.660s 4.231s 64.429us 3 3 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 1.020s 5.456s 100.473us 6 6 100.00
V2S TOTAL 9 9 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 34.351m 34.403m 40.344ms 0 7 0.00
TOTAL 100 169 59.17

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 8 53.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
77.22 95.39 84.38 89.22 58.82 86.63 93.75 32.35

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22

Failure Buckets