SRAM_CTRL/EXEC_64KB Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.720s	13.431s	4.089ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.500s	4.594s	55.893us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.500s	4.840s	53.588us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.670s	5.538s	1.427ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.530s	4.509s	21.434us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.080s	8.366s	10.019ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.500s	4.840s	53.588us	20	20	100.00
		sram_ctrl_csr_aliasing	0.530s	4.509s	21.434us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.799m	1.856m	7.056ms	4	4	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	29.520s	32.637s	16.987ms	1	1	100.00
V1		TOTAL				60	61	98.36
V2	multiple_keys	sram_ctrl_multiple_keys	13.334m	13.388m	21.427ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.741m	1.797m	4.432ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	4.078m	4.130m	33.806ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.840m	2.893m	6.060ms	3	3	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	29.590s	33.398s	136.479ms	3	3	100.00
V2	executable	sram_ctrl_executable	8.062m	8.127m	56.714ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	21.990s	25.733s	787.001us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.746m	4.797m	30.905ms	3	3	100.00
V2	max_throughput	sram_ctrl_max_throughput	11.940s	15.366s	2.133ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	2.660s	7.235s	366.426us	1	1	100.00
		sram_ctrl_throughput_w_readback	25.550s	29.189s	561.456us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.091m	7.146m	6.654ms	3	3	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.360s	6.147s	727.776us	3	3	100.00
V2	stress_all	sram_ctrl_stress_all	1.153h	1.154h	325.478ms	4	4	100.00
V2	alert_test	sram_ctrl_alert_test	0.500s	4.234s	23.013us	3	3	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.670s	6.844s	56.035us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.670s	6.844s	56.035us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.500s	4.594s	55.893us	5	5	100.00
		sram_ctrl_csr_rw	0.500s	4.840s	53.588us	20	20	100.00
		sram_ctrl_csr_aliasing	0.530s	4.509s	21.434us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.600s	4.900s	24.757us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.500s	4.594s	55.893us	5	5	100.00
		sram_ctrl_csr_rw	0.500s	4.840s	53.588us	20	20	100.00
		sram_ctrl_csr_aliasing	0.530s	4.509s	21.434us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.600s	4.900s	24.757us	20	20	100.00
V2		TOTAL				70	70	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.500s	22.600s	15.683ms	3	3	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.130s	8.314s	2.003ms	5	5	100.00
		sram_ctrl_tl_intg_err	1.950s	5.766s	1.826ms	7	7	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.130s	8.314s	2.003ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.950s	5.766s	1.826ms	7	7	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.091m	7.146m	6.654ms	3	3	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.091m	7.146m	6.654ms	3	3	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.500s	4.840s	53.588us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.062m	8.127m	56.714ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.062m	8.127m	56.714ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.062m	8.127m	56.714ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	29.590s	33.398s	136.479ms	3	3	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.550s	7.332s	6.755ms	3	3	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.500s	22.600s	15.683ms	3	3	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.310s	7.243s	1.678ms	3	3	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.720s	13.431s	4.089ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.720s	13.431s	4.089ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.062m	8.127m	56.714ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.130s	8.314s	2.003ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	29.590s	33.398s	136.479ms	3	3	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.130s	8.314s	2.003ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.130s	8.314s	2.003ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.720s	13.431s	4.089ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.130s	8.314s	2.003ms	5	5	100.00
V2S		TOTAL				21	21	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.075m	1.140m	3.396ms	4	4	100.00
V3		TOTAL				4	4	100.00
		TOTAL				155	156	99.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	17	17	17	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.12	98.75	96.46	91.19	80.00	97.32	96.38	98.70

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 6.sram_ctrl_csr_mem_rw_with_rand_reset.53313118901140545747506174535362322709663951948895403961590117813560458498907
      Line 100, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/sram_ctrl_exec_64kB-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_FATAL @ 10018963704 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
        UVM_INFO @ 10018963704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---