SRAM_CTRL/MAIN Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 25.960s 30.709s 1.126ms 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.500s 4.144s 28.758us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.520s 4.489s 25.197us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 0.950s 4.195s 243.625us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.530s 4.172s 40.329us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.070s 6.422s 396.384us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.520s 4.489s 25.197us 20 20 100.00
sram_ctrl_csr_aliasing 0.530s 4.172s 40.329us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 3.618m 3.673m 87.445ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 50.140s 53.859s 2.905ms 1 1 100.00
V1 TOTAL 58 58 100.00
V2 multiple_keys sram_ctrl_multiple_keys 9.955m 10.012m 128.375ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 2.131m 2.197m 3.097ms 1 1 100.00
V2 bijection sram_ctrl_bijection 11.189m 11.256m 28.934ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 7.752m 7.817m 30.040ms 3 3 100.00
V2 lc_escalation sram_ctrl_lc_escalation 49.660s 53.019s 13.909ms 1 1 100.00
V2 executable sram_ctrl_executable 12.432m 12.485m 42.243ms 3 3 100.00
V2 partial_access sram_ctrl_partial_access 12.830s 16.296s 1.792ms 1 1 100.00
sram_ctrl_partial_access_b2b 7.161m 7.226m 48.474ms 3 3 100.00
V2 max_throughput sram_ctrl_max_throughput 56.050s 59.088s 800.141us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.320s 8.069s 699.613us 1 1 100.00
sram_ctrl_throughput_w_readback 39.340s 42.720s 883.440us 1 1 100.00
V2 regwen sram_ctrl_regwen 4.580m 4.645m 10.286ms 3 3 100.00
V2 ram_cfg sram_ctrl_ram_cfg 1.980s 5.092s 2.398ms 3 3 100.00
V2 stress_all sram_ctrl_stress_all 44.564m 44.631m 360.855ms 5 5 100.00
V2 alert_test sram_ctrl_alert_test 0.490s 4.076s 17.753us 3 3 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 3.310s 6.411s 564.587us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 3.310s 6.411s 564.587us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.500s 4.144s 28.758us 5 5 100.00
sram_ctrl_csr_rw 0.520s 4.489s 25.197us 20 20 100.00
sram_ctrl_csr_aliasing 0.530s 4.172s 40.329us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.570s 4.524s 25.938us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.500s 4.144s 28.758us 5 5 100.00
sram_ctrl_csr_rw 0.520s 4.489s 25.197us 20 20 100.00
sram_ctrl_csr_aliasing 0.530s 4.172s 40.329us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.570s 4.524s 25.938us 20 20 100.00
V2 TOTAL 71 71 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 32.990s 36.340s 14.106ms 5 5 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.290s 7.069s 1.740ms 5 5 100.00
sram_ctrl_tl_intg_err 1.900s 5.180s 404.245us 5 5 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.290s 7.069s 1.740ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 1.900s 5.180s 404.245us 5 5 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 4.580m 4.645m 10.286ms 3 3 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 4.580m 4.645m 10.286ms 3 3 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.520s 4.489s 25.197us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 12.432m 12.485m 42.243ms 3 3 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 12.432m 12.485m 42.243ms 3 3 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 12.432m 12.485m 42.243ms 3 3 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 49.660s 53.019s 13.909ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 4.130s 8.082s 3.046ms 3 3 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 32.990s 36.340s 14.106ms 5 5 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 3.500s 7.103s 3.482ms 4 4 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 25.960s 30.709s 1.126ms 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 25.960s 30.709s 1.126ms 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 12.432m 12.485m 42.243ms 3 3 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.290s 7.069s 1.740ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 49.660s 53.019s 13.909ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.290s 7.069s 1.740ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.290s 7.069s 1.740ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 25.960s 30.709s 1.126ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.290s 7.069s 1.740ms 5 5 100.00
V2S TOTAL 22 22 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 48.630s 51.752s 1.418ms 8 8 100.00
V3 TOTAL 8 8 100.00
TOTAL 159 159 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 17 17 17 100.00
V2S 5 5 5 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.38 98.75 96.34 85.98 80.00 97.32 96.38 98.89

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22