SRAM_CTRL/RET Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 33.040s 37.130s 137.338us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.510s 4.171s 113.133us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.530s 4.380s 192.758us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.710s 5.241s 847.260us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.550s 4.298s 18.857us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 1.950s 5.433s 231.416us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.530s 4.380s 192.758us 20 20 100.00
sram_ctrl_csr_aliasing 0.550s 4.298s 18.857us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 8.360s 11.425s 2.606ms 3 3 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.330s 6.173s 374.827us 1 1 100.00
V1 TOTAL 60 60 100.00
V2 multiple_keys sram_ctrl_multiple_keys 3.784m 3.850m 28.032ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 3.070m 3.134m 5.774ms 1 1 100.00
V2 bijection sram_ctrl_bijection 30.570s 34.790s 865.228us 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 11.180m 11.235m 18.054ms 3 3 100.00
V2 lc_escalation sram_ctrl_lc_escalation 8.920s 12.578s 14.137ms 3 3 100.00
V2 executable sram_ctrl_executable 13.135m 13.202m 98.369ms 3 3 100.00
V2 partial_access sram_ctrl_partial_access 7.230s 10.578s 199.453us 1 1 100.00
sram_ctrl_partial_access_b2b 6.131m 6.193m 22.439ms 3 3 100.00
V2 max_throughput sram_ctrl_max_throughput 14.160s 17.878s 182.799us 1 1 100.00
sram_ctrl_throughput_w_partial_write 0.760s 4.358s 152.569us 1 1 100.00
sram_ctrl_throughput_w_readback 44.470s 48.174s 287.136us 1 1 100.00
V2 regwen sram_ctrl_regwen 10.008m 10.072m 51.575ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.550s 4.150s 37.832us 3 3 100.00
V2 stress_all sram_ctrl_stress_all 26.676m 26.747m 40.744ms 6 6 100.00
V2 alert_test sram_ctrl_alert_test 0.490s 4.237s 98.372us 3 3 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 3.430s 7.263s 159.540us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 3.430s 7.263s 159.540us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.510s 4.171s 113.133us 5 5 100.00
sram_ctrl_csr_rw 0.530s 4.380s 192.758us 20 20 100.00
sram_ctrl_csr_aliasing 0.550s 4.298s 18.857us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.600s 4.457s 108.600us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.510s 4.171s 113.133us 5 5 100.00
sram_ctrl_csr_rw 0.530s 4.380s 192.758us 20 20 100.00
sram_ctrl_csr_aliasing 0.550s 4.298s 18.857us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.600s 4.457s 108.600us 20 20 100.00
V2 TOTAL 72 72 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 2.290s 6.107s 1.449ms 3 3 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.230s 7.107s 353.865us 5 5 100.00
sram_ctrl_tl_intg_err 1.710s 5.210s 2.059ms 6 6 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.230s 7.107s 353.865us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 1.710s 5.210s 2.059ms 6 6 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 10.008m 10.072m 51.575ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 10.008m 10.072m 51.575ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.530s 4.380s 192.758us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 13.135m 13.202m 98.369ms 3 3 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 13.135m 13.202m 98.369ms 3 3 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 13.135m 13.202m 98.369ms 3 3 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 8.920s 12.578s 14.137ms 3 3 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 0.750s 5.120s 87.335us 3 3 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 2.290s 6.107s 1.449ms 3 3 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 0.770s 4.160s 131.459us 4 4 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 33.040s 37.130s 137.338us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 33.040s 37.130s 137.338us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 13.135m 13.202m 98.369ms 3 3 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.230s 7.107s 353.865us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 8.920s 12.578s 14.137ms 3 3 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.230s 7.107s 353.865us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.230s 7.107s 353.865us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 33.040s 37.130s 137.338us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.230s 7.107s 353.865us 5 5 100.00
V2S TOTAL 21 21 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 1.660m 1.729m 3.136ms 4 4 100.00
V3 TOTAL 4 4 100.00
TOTAL 157 157 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 17 17 17 100.00
V2S 5 5 5 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.34 98.70 96.46 85.90 80.00 97.26 96.35 98.70

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22