SYSRST_CTRL Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.000s 5.024s 2.140ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 4.230s 8.136s 2.446ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 4.390s 8.342s 2.245ms 5 5 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.950s 8.190s 2.503ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 11.090s 14.643s 6.020ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 4.350s 8.012s 2.032ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 2.674m 2.738m 71.813ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 5.080s 8.396s 2.227ms 3 3 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 4.290s 8.304s 2.062ms 3 3 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 4.350s 8.012s 2.032ms 20 20 100.00
sysrst_ctrl_csr_aliasing 5.080s 8.396s 2.227ms 3 3 100.00
V1 TOTAL 48 48 100.00
V2 combo_detect sysrst_ctrl_combo_detect 4.731m 4.782m 152.673ms 9 9 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 3.759m 3.826m 137.891ms 28 28 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 5.470s 9.308s 3.001ms 3 3 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 7.290s 11.051s 3.838ms 10 10 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 4.960s 8.318s 2.508ms 3 3 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 1.400s 5.233s 2.192ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 6.640s 10.273s 3.328ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 1.640s 5.212s 2.627ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 4.493m 4.546m 1.668s 6 6 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 54.800s 58.617s 32.626ms 4 4 100.00
V2 stress_all sysrst_ctrl_stress_all 5.810m 5.861m 203.711ms 22 22 100.00
V2 alert_test sysrst_ctrl_alert_test 1.320s 5.179s 2.034ms 3 3 100.00
V2 intr_test sysrst_ctrl_intr_test 4.110s 8.048s 2.007ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 4.520s 8.443s 2.021ms 4 4 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 4.520s 8.443s 2.021ms 4 4 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 11.090s 14.643s 6.020ms 5 5 100.00
sysrst_ctrl_csr_rw 4.350s 8.012s 2.032ms 20 20 100.00
sysrst_ctrl_csr_aliasing 5.080s 8.396s 2.227ms 3 3 100.00
sysrst_ctrl_same_csr_outstanding 13.570s 16.767s 7.505ms 3 3 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 11.090s 14.643s 6.020ms 5 5 100.00
sysrst_ctrl_csr_rw 4.350s 8.012s 2.032ms 20 20 100.00
sysrst_ctrl_csr_aliasing 5.080s 8.396s 2.227ms 3 3 100.00
sysrst_ctrl_same_csr_outstanding 13.570s 16.767s 7.505ms 3 3 100.00
V2 TOTAL 148 148 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 38.810s 42.262s 42.047ms 3 3 100.00
sysrst_ctrl_tl_intg_err 1.221m 1.282m 42.411ms 4 4 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.221m 1.282m 42.411ms 4 4 100.00
V2S TOTAL 7 7 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 11.880s 15.180s 6.549ms 7 7 100.00
V3 TOTAL 7 7 100.00
TOTAL 210 210 100.00

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 15 15 15 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.80 99.40 97.98 100.00 94.87 99.48 98.18 87.69

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22