UART Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.170s	4.645s	481.827us	3	3	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.430s	4.253s	16.788us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.460s	4.250s	15.129us	3	3	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.710s	5.294s	1.024ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.540s	4.244s	33.577us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.900s	4.718s	30.054us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.460s	4.250s	15.129us	3	3	100.00
		uart_csr_aliasing	0.540s	4.244s	33.577us	5	5	100.00
V1		TOTAL				41	41	100.00
V2	base_random_seq	uart_tx_rx	2.146m	2.207m	113.402ms	5	5	100.00
V2	parity	uart_smoke	1.170s	4.645s	481.827us	3	3	100.00
		uart_tx_rx	2.146m	2.207m	113.402ms	5	5	100.00
V2	parity_error	uart_intr	1.009m	1.069m	64.549ms	5	5	100.00
		uart_rx_parity_err	37.470s	41.486s	38.605ms	3	3	100.00
V2	watermark	uart_tx_rx	2.146m	2.207m	113.402ms	5	5	100.00
		uart_intr	1.009m	1.069m	64.549ms	5	5	100.00
V2	fifo_full	uart_fifo_full	4.427m	4.513m	310.548ms	9	9	100.00
V2	fifo_overflow	uart_fifo_overflow	5.051m	5.129m	284.876ms	5	5	100.00
V2	fifo_reset	uart_fifo_reset	4.742m	4.798m	251.247ms	51	51	100.00
V2	rx_frame_err	uart_intr	1.009m	1.069m	64.549ms	5	5	100.00
V2	rx_break_err	uart_intr	1.009m	1.069m	64.549ms	5	5	100.00
V2	rx_timeout	uart_intr	1.009m	1.069m	64.549ms	5	5	100.00
V2	perf	uart_perf	1.459m	1.524m	12.992ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.630s	5.795s	3.391ms	1	1	100.00
V2	line_loopback	uart_loopback	2.630s	5.795s	3.391ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	3.190s	6.660s	4.986ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.480s	6.770s	5.211ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.850s	6.702s	1.257ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	6.870s	10.429s	4.944ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	10.832m	10.896m	135.916ms	5	5	100.00
V2	stress_all	uart_stress_all	6.951m	7.015m	176.480ms	10	10	100.00
V2	alert_test	uart_alert_test	0.410s	4.291s	13.515us	3	3	100.00
V2	intr_test	uart_intr_test	0.470s	4.503s	11.342us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.670s	5.414s	327.829us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.670s	5.414s	327.829us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.430s	4.253s	16.788us	5	5	100.00
		uart_csr_rw	0.460s	4.250s	15.129us	3	3	100.00
		uart_csr_aliasing	0.540s	4.244s	33.577us	5	5	100.00
		uart_same_csr_outstanding	0.560s	4.440s	16.697us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.430s	4.253s	16.788us	5	5	100.00
		uart_csr_rw	0.460s	4.250s	15.129us	3	3	100.00
		uart_csr_aliasing	0.540s	4.244s	33.577us	5	5	100.00
		uart_same_csr_outstanding	0.560s	4.440s	16.697us	20	20	100.00
V2		TOTAL				191	192	99.48
V2S	tl_intg_err	uart_sec_cm	0.590s	4.677s	38.613us	3	3	100.00
		uart_tl_intg_err	0.940s	4.222s	98.007us	4	4	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.940s	4.222s	98.007us	4	4	100.00
V2S		TOTAL				7	7	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.800m	1.864m	5.406ms	9	10	90.00
V3		TOTAL				9	10	90.00
		TOTAL				248	250	99.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.54	99.48	98.25	74.67	--	98.14	97.12	99.57

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.63705211295260104837508199005265215011404703855801520006114549051599722332182
      Line 77, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 1644559652 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 1644559652 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1644559652 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 2080365179 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5,                                 clk_pulses: 0
        UVM_ERROR @ 2080406845 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (212 [0xd4] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 8.uart_stress_all_with_rand_reset.90224651534213859307411707238922750000611784313990267844785573237925964493970
      Line 168, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1992530578 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1992888462 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_INFO @ 2079149032 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/672
        UVM_INFO @ 2154283620 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/672
        UVM_ERROR @ 2171241006 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0