USBDEV Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.670s 4.433s 214.924us 1 1 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.710s 5.082s 270.223us 5 5 100.00
V1 csr_rw usbdev_csr_rw 0.750s 5.169s 83.750us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 5.730s 10.013s 925.063us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 2.000s 7.280s 147.776us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 1.760s 5.296s 94.562us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 0.750s 5.169s 83.750us 20 20 100.00
usbdev_csr_aliasing 2.000s 7.280s 147.776us 5 5 100.00
V1 mem_walk usbdev_mem_walk 2.640s 7.290s 171.998us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 1.490s 5.086s 104.894us 5 5 100.00
V1 TOTAL 66 66 100.00
V2 in_trans usbdev_in_trans 0.660s 4.421s 199.916us 1 1 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 1.060s 4.537s 526.279us 1 1 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.490s 4.413s 46.814us 4 4 100.00
V2 av_buffer usbdev_av_buffer 0.590s 4.644s 158.822us 1 1 100.00
V2 rx_fifo usbdev_pkt_buffer 22.810s 26.326s 14.379ms 4 4 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 0.770s 4.361s 314.548us 4 4 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.590s 4.294s 148.312us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 0.610s 4.327s 175.990us 1 1 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 0.690s 4.521s 219.103us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 0.720s 4.324s 220.468us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 0.740s 4.356s 254.144us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.590s 4.417s 169.307us 3 3 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 0.640s 4.300s 214.250us 1 1 100.00
usbdev_stream_len_max 0.730s 4.312s 276.776us 1 1 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 0.690s 4.312s 279.221us 1 1 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.560s 4.244s 150.717us 1 1 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.610s 4.256s 193.913us 1 1 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 0.610s 4.423s 184.868us 1 1 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 0.660s 4.421s 238.407us 1 1 100.00
V2 out_stall usbdev_out_stall 0.630s 4.317s 199.317us 1 1 100.00
V2 in_stall usbdev_in_stall 0.550s 4.627s 136.883us 1 1 100.00
V2 out_iso usbdev_out_iso 0.590s 4.344s 144.632us 1 1 100.00
V2 in_iso usbdev_in_iso 0.740s 4.636s 224.977us 1 1 100.00
V2 pkt_received usbdev_pkt_received 0.630s 4.501s 190.812us 3 3 100.00
V2 pkt_sent usbdev_pkt_sent 0.660s 4.458s 208.793us 1 1 100.00
V2 disconnected usbdev_disconnected 0.580s 4.609s 142.699us 3 3 100.00
V2 host_lost usbdev_host_lost 6.670s 10.637s 4.167ms 4 4 100.00
V2 link_reset usbdev_link_reset 0.590s 4.420s 190.426us 4 4 100.00
V2 link_suspend usbdev_link_suspend 10.110s 13.713s 10.838ms 4 4 100.00
V2 link_resume usbdev_link_resume 19.690s 23.141s 27.308ms 3 3 100.00
V2 av_empty usbdev_av_empty 0.690s 4.633s 178.577us 5 5 100.00
V2 rx_full usbdev_rx_full 0.850s 4.448s 422.564us 5 5 100.00
V2 av_overflow usbdev_av_overflow 0.630s 4.604s 192.493us 4 4 100.00
V2 link_in_err usbdev_link_in_err 0.650s 4.374s 219.617us 1 1 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.590s 4.399s 149.116us 3 3 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.640s 4.424s 249.320us 3 3 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.590s 4.571s 198.674us 3 3 100.00
V2 link_out_err usbdev_link_out_err 1.030s 4.365s 546.022us 3 3 100.00
V2 enable usbdev_enable 0.590s 4.537s 64.250us 1 1 100.00
V2 resume_link_active usbdev_resume_link_active 19.740s 23.217s 20.162ms 20 20 100.00
V2 device_address usbdev_device_address 23.050s 26.908s 22.896ms 6 6 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 0.960s 4.589s 471.713us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.610s 4.409s 156.528us 1 1 100.00
V2 endpoint_access usbdev_endpoint_access 1.560s 4.528s 976.224us 1 1 100.00
V2 disable_endpoint usbdev_disable_endpoint 1.180s 4.622s 659.580us 1 1 100.00
V2 endpoint_types usbdev_endpoint_types 1.180s 5.913s 634.801us 50 50 100.00
V2 out_trans_nak usbdev_out_trans_nak 0.600s 4.330s 159.244us 1 1 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.580s 4.450s 155.557us 1 1 100.00
V2 nak_trans usbdev_nak_trans 0.670s 4.286s 274.709us 3 3 100.00
V2 stall_trans usbdev_stall_trans 0.590s 4.404s 179.690us 1 1 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 0.750s 4.609s 307.331us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0.640s 4.412s 216.456us 3 3 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.600s 4.305s 155.360us 1 1 100.00
V2 streaming_test usbdev_streaming_out 13.020s 16.336s 2.074ms 1 1 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 1.809m 1.875m 114.203ms 5 5 100.00
usbdev_freq_loclk 1.843m 1.910m 116.114ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 2.254m 2.309m 116.248ms 3 3 100.00
usbdev_freq_loclk_max 1.773m 1.840m 116.182ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 2.015m 2.074m 120.112ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 12.080s 15.320s 1.991ms 1 1 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 10.930s 14.109s 2.351ms 1 1 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 9.720s 13.688s 712.189us 1 1 100.00
V2 device_timeout usbdev_device_timeout 33.370s 36.396s 8.406ms 3 3 100.00
V2 packet_buffer usbdev_pkt_buffer 22.810s 26.326s 14.379ms 4 4 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0.970s 4.291s 541.161us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 23.880s 27.097s 30.631ms 4 4 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 17.820s 22.751s 19.150ms 3 3 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 8.800s 14.003s 11.683ms 3 3 100.00
V2 invalid_sync usbdev_invalid_sync 1.128m 1.181m 3.851ms 3 3 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 15.700s 19.645s 2.730ms 1 1 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 1.540m 1.599m 5.239ms 6 6 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 3.486m 3.563m 15.476ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 1.939m 2.015m 7.309ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 3.193m 3.264m 13.834ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 54.670s 58.436s 3.143ms 25 25 100.00
usbdev_max_usb_traffic 49.570s 53.257s 2.799ms 3 3 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 2.547m 2.620m 11.947ms 6 6 100.00
V2 in_packet_retraction usbdev_iso_retraction 48.730s 52.802s 11.889ms 3 3 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 1.930s 5.659s 1.239ms 6 6 100.00
V2 setup_priority usbdev_setup_priority 0.930s 4.405s 425.171us 3 3 100.00
V2 fifo_resets usbdev_fifo_rst 1.990s 5.803s 531.881us 1 1 100.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 1.120s 5.907s 556.080us 10 10 100.00
V2 fifo_levels usbdev_fifo_levels 0.840s 5.448s 317.971us 46 46 100.00
V2 rxenable_out_conditional usbdev_rxenable_out 0.600s 4.486s 163.477us 5 5 100.00
V2 intr_test usbdev_intr_test 0.580s 5.095s 48.235us 5 5 100.00
V2 alert_test usbdev_alert_test 0.480s 4.510s 38.285us 3 3 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 2.460s 7.195s 292.840us 5 5 100.00
V2 tl_d_illegal_access usbdev_tl_errors 2.460s 7.195s 292.840us 5 5 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.710s 5.082s 270.223us 5 5 100.00
usbdev_csr_rw 0.750s 5.169s 83.750us 20 20 100.00
usbdev_csr_aliasing 2.000s 7.280s 147.776us 5 5 100.00
usbdev_same_csr_outstanding 1.060s 4.914s 415.512us 3 3 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.710s 5.082s 270.223us 5 5 100.00
usbdev_csr_rw 0.750s 5.169s 83.750us 20 20 100.00
usbdev_csr_aliasing 2.000s 7.280s 147.776us 5 5 100.00
usbdev_same_csr_outstanding 1.060s 4.914s 415.512us 3 3 100.00
V2 TOTAL 388 388 100.00
V2S tl_intg_err usbdev_sec_cm 1.720s 5.318s 1.717ms 3 3 100.00
usbdev_tl_intg_err 3.740s 9.471s 1.118ms 7 7 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 3.740s 9.471s 1.118ms 7 7 100.00
V2S TOTAL 10 10 100.00
V3 dpi_config_host usbdev_dpi_config_host 1.487m 1.551m 5.109ms 3 3 100.00
V3 TOTAL 3 3 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.490s 5.852s 23.099us 0 10 0.00
usbdev_stress_all 0.380s 4.357s 0 1 0.00
TOTAL 467 478 97.70

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 87 87 87 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.88 98.79 95.53 97.23 93.22 98.34 96.20 98.82

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22

Failure Buckets